Erik Jung

Stackable packages with integrated components

A technology for the integration of thin chips into build-up layers of organic substrates is under development. In order to improve the process, laser technology has been introduced for via drilling and interconnect structuring. Basic reliability tests of embedded chips were performed. For the realization of integrated resistors, the deposition of ultra-thin electroless Ni layers is used. Also here, laser ablation has been implemented for structuring. Finally, an improved and simplified concept for the realization of stackable chip packages is presented.

Through silicon vias as enablers for 3D systems

This special session on 3D TSVpsilas will highlight some of the fabrication processes and used technologies to create vias from the frontside of an active circuit to its backside and potential implementation solutions to form complex systems leveraging these novel possibilities. General techniques for via formation are discussed as well as advanced integration solutions leveraging the power of 3D TSVpsilas.

Processing design rules for reliable reflowable underfill application

Recently there has been a growing interest in reflowable underfill materials for flip chip processes as a way to increase productivity - especially in consumer products or applications with a high degree of miniaturization. Former investigations had shown that the reliability obtained with commercially available products still needs improvement. Therefore it is especially important to observe the progress made in material development and to establish optimized processes. The scope of this work is the characterization and evaluation of different currently available reflowable underfill materials for optimized flip chip processes. A method is developed for the analysis of the underfillers that can be used for a standardized incoming inspection and preliminary process specification. It includes the determination of material properties (cure behavior, Tg, CTE, modulus) as well as the investigation of the flow behavior during placement. This is realized by a special test vehicle which carries structures that can simulate certain typical board characteristics (topography of solder mask, vias, conductor lines) under the die. The influence of these structures together with process parameters like deposition pattern, placement temperature and placement speed is studied. This analysis is a fast way to obtain the data required for optimizing the process flow for the materials chosen and for establishing basic design rules. With the processes defined from these results test samples with Daisy Chain structures are assembled. Solder joint formation and quality of the underfill layer are the criteria which are evaluated by X-ray, CSAM and cross sectioning. Together with the material properties these results allow the definition of design rules for flip chip processes using reflowable underfill. In order to verify the results and evaluate the underfillers selected the samples are then subjected to thermal cycling and humidity testing to determine the reliability obtained. The results allow a comparison with standard underfill materials and a statement on the applicability for production.

Three Dimensional Packaging of Bare IC Into Printed Circuit Boards for SIP

The demand to miniaturize products especially for mobile applications and autonomous systems is continuing to drive the evolution of electronic products and manufacturing methods. To further the miniaturization of future products the integration of functions on miniaturized subsystems, i.e. System-in-Package (SiP) is a promising approach. Here, use of recent manufacturing methods allows to merge the SiP concept with a volumetric integration of IC’s. Up to now, most of the systems make use of single- or double-sided populated system carriers. A new challenge is to incorporate not only passive components, but as well active circuitry (IC’s) and the necessary thermal management. Ultra thin chips (i.e. silicon dies thinned down to <50μm total thickness) lend themselves to reach these goals. Chips with that thickness can be embedded in the dielectric layers of modern laminate PCB’s. Micro via technology allows to contact the embedded chip to the outer faces of the system circuitry. The aspects of embedding and making the electrical contact as well as the thermal management are highlighted. Results on FEM simulations and technical achievements are presented.Copyright

Chip in Polymer: 3D Integration of Active Circuitry in Polymeric Substrate

The demand to miniaturize products especially for mobile applications and autonomous systems is continuing to drive the evolution of electronic products and manufacturing methods. One key to miniaturization developed in the past was the use of unpackaged, bare dice. Saving the volume and weight of the package, significant reduction in footprint was achieved. A next step conceived to further the miniaturization is the integration of functions on miniaturized subsystems, i.e. System-in-Package (SiP), in contrast to a full silicon integration (System-on-Chip, SoC). Here, use of recent manufacturing methods allows to merge the SiP approach with a volumetric integration. Up to now, most of the systems make use of single- or double-sided populated system carriers. Embedding of passive components was a first step forward. A new challenge is to incorporate not only passive components, but as well active circuitry (IC’s) and the necessary thermal management. Ultra thin chips (i.e. silicon dies thinned down to <50μm total thickness) lend themselves to reach these goals. Chips with that thickness can be embedded in the dielectric layers of modern laminate PCB’s. Micro via technology allows to contact the embedded chip to the outer faces of the system circuitry. As a ultimate goal for microsystem integration, the embedding of optical and fluidical system components can be envisioned. This paper presents the first attempts to embed thin silicon dies in to polymeric system carriers. The aspects of embedding and making the electrical contact as well as the thermal management are highlighted. To reach the goal of a vertically stackable “box-of-bricks” type of ultra thin (UT) package, thin silicon chips are embedded and interconnected on a peripheral UT-CSP.© 2003 ASME

A new approach for system integrated packaging

As the number of applications for flexible assemblies is growing there is also a larger variation of requirements for such packages. Therefore, different technologies from CSPs to smart cards have been developed. This paper describes the results of the development of a new approach to wafer-level redistribution as well as packaging concepts for CSPs and embedding of ultra-thin ICs into laminated substrates. The electrical interconnection is made by fully-additive deposition of Cu lines. The technology is based on wet-chemical treatments which enable the avoidance of expensive vacuum processes and electroplating. A photo-sensitive epoxy material, commonly used in printed circuit board manufacturing, was chosen as dielectric. Furthermore, the process implements electroless Ni deposition to protect the Al bond pads and to act as a solder diffusion barrier on the Cu lines. The technologies are presented together with the important parameters and typical results achieved. In order to evaluate the applicability of the processes developed, the reliability data of the obtained assemblies is presented and compared.