A. Neumann

Integration of passive and active components into build-up layers

In the last few years, an increasing number of mobile electronic products have been launched to the market, like mobile communicators, combining the RF functions of a mobile phone and the complexity of a palm top computer. Inside these devices there is less and less space for the electronic system, while packaging density and operating frequencies are constantly increasing. Additionally, the product life time is going down, requiring short design cycles and a production at low-cost based on well established technologies. These trends are a strong challenge for microelectronic packaging and assembly technology. An advanced packaging concept is presented, the chip in polymer technology, which aims to face the above mentioned challenges. It is based on the embedding of ultra thin semiconductor chips into the build-up layers of printed circuit boards together with integrated passive components. Processing issues with regard to registration tolerances between embedded chips and metal lines are discussed. First results of the formation of integrated resistors are shown, using electrolessly deposited NiP layers. The embedding technology is put into relation to common interconnection technologies regarding expected RF properties and system design aspects. Basic thermomechanical properties of a first technology demonstrator, a stackable chip scale package, is discussed using finite element modeling.

Smart PCBs manufacturing technologies

The inherent functionality of a printed wiring board can be dramatically increased by embedding electronic components into the board. For resistors, capacitors and inductors technological turnkey solutions are offered by major manufacturers and also technologies are under development. Application examples for passives integration into flexible PCBs are given. A further boost of functionality is accomplished by the integration of active chips into the board. An overview of different approaches and the respective sets of enabling technologies for the integration of chips into the board are given. Two of the approaches for the chip integration into the board are discussed in detail. A prerequisite for those technologies is the chip thinning, which is now available as a commercial service for chip thicknesses down to 20 /spl mu/m. In the chip in polymer (CIP) approach the thin chip is precisely positioned and soundly attached onto the board surface. After lamination of a copper coated resin foil via contacts are drilled through the laminate to the contact pads of the chip. The transfer of precise chip position parameters with respect to the board is essential for this step. The wiring on the laminate foil to the chip and to other components is subsequently structured. Process parameters and results are presented. For the embedding of chips into flexible PCBs the chip is flipped onto the substrate surface and thermode bonded. The process implies soldering. Therefore electroless Ni(P) is deposited onto the Al bond pads of the chip which is subsequently covered with small caps of solder. The solder cap heights are in the range of 4 to 8 /spl mu/m in order to keep the interconnection height low. The solder joint is realized by thermode bonding of the chip onto the structured wiring of the substrate using no-flow underfiller. The chip containing layer is then laminated and contacted to outer layers of the board by conventional through hole technique. An assessment of the advantages and disadvantages of both approaches are given on the status of our present understanding of the technological challenges.

Process flow and manufacturing concept for embedded active devices

The development of smaller, lighter and thinner packages with larger and higher pin count ICs and better performance will play an enormously important role in the future for portable electronic products. Additionally the product life time is going down, requiring short design cycles and a production at low-cost based on well established technologies. These trends are a strong challenge for microelectronic packaging and assembly technology. A chip embedding technology for stackable packages was developed at the joined institute of Fraunhofer IZM and the Technical University of Berlin the so-called chip in polymer (CIP) process. Its main feature is the embedding of very thin chips (50 /spl mu/m thickness or less) into build-up layers of printed circuit boards (PCBs), which does not sacrifice any space in the core substrate. The embedded chips can be combined with integrated passive components. A substantial advantage of the CIP approach is the embedding of components, using mainly processes and equipment from advanced PCB manufacturing. The scope of this paper is the presentation of the chip in polymer technology regarding technological and economical aspects and to discuss the effect on a new value chain.

Stackable packages with integrated components

A technology for the integration of thin chips into build-up layers of organic substrates is under development. In order to improve the process, laser technology has been introduced for via drilling and interconnect structuring. Basic reliability tests of embedded chips were performed. For the realization of integrated resistors, the deposition of ultra-thin electroless Ni layers is used. Also here, laser ablation has been implemented for structuring. Finally, an improved and simplified concept for the realization of stackable chip packages is presented.

Three Dimensional Packaging of Bare IC Into Printed Circuit Boards for SIP

The demand to miniaturize products especially for mobile applications and autonomous systems is continuing to drive the evolution of electronic products and manufacturing methods. To further the miniaturization of future products the integration of functions on miniaturized subsystems, i.e. System-in-Package (SiP) is a promising approach. Here, use of recent manufacturing methods allows to merge the SiP concept with a volumetric integration of IC’s. Up to now, most of the systems make use of single- or double-sided populated system carriers. A new challenge is to incorporate not only passive components, but as well active circuitry (IC’s) and the necessary thermal management. Ultra thin chips (i.e. silicon dies thinned down to <50μm total thickness) lend themselves to reach these goals. Chips with that thickness can be embedded in the dielectric layers of modern laminate PCB’s. Micro via technology allows to contact the embedded chip to the outer faces of the system circuitry. The aspects of embedding and making the electrical contact as well as the thermal management are highlighted. Results on FEM simulations and technical achievements are presented.Copyright

Chip in Polymer: 3D Integration of Active Circuitry in Polymeric Substrate

The demand to miniaturize products especially for mobile applications and autonomous systems is continuing to drive the evolution of electronic products and manufacturing methods. One key to miniaturization developed in the past was the use of unpackaged, bare dice. Saving the volume and weight of the package, significant reduction in footprint was achieved. A next step conceived to further the miniaturization is the integration of functions on miniaturized subsystems, i.e. System-in-Package (SiP), in contrast to a full silicon integration (System-on-Chip, SoC). Here, use of recent manufacturing methods allows to merge the SiP approach with a volumetric integration. Up to now, most of the systems make use of single- or double-sided populated system carriers. Embedding of passive components was a first step forward. A new challenge is to incorporate not only passive components, but as well active circuitry (IC’s) and the necessary thermal management. Ultra thin chips (i.e. silicon dies thinned down to <50μm total thickness) lend themselves to reach these goals. Chips with that thickness can be embedded in the dielectric layers of modern laminate PCB’s. Micro via technology allows to contact the embedded chip to the outer faces of the system circuitry. As a ultimate goal for microsystem integration, the embedding of optical and fluidical system components can be envisioned. This paper presents the first attempts to embed thin silicon dies in to polymeric system carriers. The aspects of embedding and making the electrical contact as well as the thermal management are highlighted. To reach the goal of a vertically stackable “box-of-bricks” type of ultra thin (UT) package, thin silicon chips are embedded and interconnected on a peripheral UT-CSP.© 2003 ASME