Karl Fritz

Autonomous bit error rate testing at multi-gbit/s rates implemented in a 5AM SiGe circuit for radiation effects self test (CREST)

SEE testing at multi-Gbit/s data rates has traditionally involved elaborate high speed test equipment setups for at-speed testing. We demonstrate a generally applicable self test circuit approach implemented in IBMs 5AM SiGe process, and describe its ability to capture complex error signatures during circuit operation at data rates exceeding 5 Gbit/s. Comparisons of data acquired with FPGA control of the CREST ASIC versus conventional bit error rate test equipment validate the approach. In addition, we describe SEE characteristics of the IBM 5AM process implemented in five variations of the D flip-flop based serial register. Heavy ion SEE data acquired at angles follow the traditional RPP-based analysis approach in one case, but deviate by orders on magnitude in others, even though all circuits are implemented in the same 5AM SiGe HBT process.

Heavy-ion broad-beam and microprobe studies of single-event upsets in 0.20-/spl mu/m SiGe heterojunction bipolar transistors and circuits

Combining broad-beam circuit level single-event upset (SEU) response with heavy ion microprobe charge collection measurements on single silicon-germanium heterojunction bipolar transistors improves understanding of the charge collection mechanisms responsible for SEU response of digital SiGe HBT technology. This new understanding of the SEU mechanisms shows that the right rectangular parallel-piped model for the sensitive volume is not applicable to this technology. A new first-order physical model is proposed and calibrated with moderate success.

An SEU hardening approach for high-speed SiGe HBT digital logic

A new circuit-level single-event upset (SEU) hardening approach for high-speed SiGe HBT current-steering digital logic is introduced and analyzed using both device and circuit simulations. The workhorse D-type flip-flop circuit architecture is modified in order to significantly improve its SEU immunity. Partial elimination of the effect of cross-coupling at the transistor level in the storage cell of this new circuit decreases its vulnerability to SEU. The SEU response of this new circuit is quantitatively compared with three other D flip-flop architectures, including the unhardened circuit, a conventional NAND gate based circuit, and a current-sharing hardened (CSH) circuit, at both variable data rate and switching current. The new circuit shows substantial improvement in SEU response over the unhardened version, with little increase in layout complexity and power consumption. While the NAND gate based circuit still shows better SEU response than the other circuits, its high power consumption will preclude its use in space applications. Our results suggest that this new circuit architecture exhibits sufficient SEU tolerance, low layout complexity, and modest power consumption, and thus should prove suitable for many space applications requiring very high-speed digital logic.

A comparative study of heavy-ion and proton-induced bit-error sensitivity and complex burst-error modes in commercially available high-speed SiGe BiCMOS

We compare heavy ion and proton SEE data on commercial SiGe technologies from IBMs 7 HP and 5 AM processes and Jazz Semiconductors SiGe120 process at data rates from 50Mb/s to 12.4 Gb/s. Complex burst-error trends correlate with both data rate and particle LET, as well as pulsed laser probing of both data paths and clock distribution circuitry.

A 20 GS/s 5-Bit SiGe BiCMOS Dual-Nyquist Flash ADC With Sampling Capability up to 35 GS/s Featuring Offset Corrected Exclusive-Or Comparators

The design and wafer probe test results of a 5-bit SiGe flash ADC are presented. The integrated circuit, fabricated in a 200/250 GHz fT/Fmax, SiGe BiCMOS technology, provides a 5-bit analog to digital conversion with dual Nyquist operation at sample frequencies up to 20 GHz. Sampling clock rates are demonstrated as high as 35 GS/s. The ADC makes use of a comparator with an integrated exclusive-or function to reduce power consumption. The device also generates two half-rate interleaved outputs to ease data capture with laboratory equipment. An effective number of bits (ENOB) of nearly 5.0 is achieved for low-frequency input tones, dropping to 4.0 at 10 GHz.

A 20Gb/s SerDes transmitter with adjustable source impedance and 4-tap feed-forward equalization in 65nm bulk CMOS

The design and wafer probe test results of a 20 Gb/s Source-Series Terminated SerDes transmitter are presented. The integrated circuit, fabricated in a 65 nm bulk CMOS technology, transmits pre-emphasized data through the use of a 4-tap feed-forward equalizer. Transmitter output impedance is adjustable from 45 to 55 ohms. A power consumption of 167 mW at 1.1 V was measured at a transmit rate of 20 Gb/s.

A highly parallel AES-GCM core for authenticated encryption of 400 Gb/s network protocols

The Advanced Encryption Standard (AES) together with the Galois Counter Mode (GCM) of operation has been approved for use in several high throughput network protocols to provide authenticated encryption. However, the demand for continued increase in network bandwidth has not abated and we anticipate the need for continual performance improvement of AES-GCM in hardware. Additionally, as data interfaces become wider and segmented, existing methods of GCM parallelization become inefficient. This paper presents a novel scalable architecture for highly parallel implementations of AES-GCM that can process multiple separately-keyed packets simultaneously every clock cycle. We demonstrate throughputs of 482 Gb/s in a single Xilinx Virtex Ultrascale FPGA and describe how the architecture can be used to achieve over 800 Gb/s in a system comprising multiple FPGAs.

A 70 Gbps 16:1 Multiplexer and a 60 Gbps 1:16 Demultiplexer in a SiGe BiCMOS Technology

The authors present circuits for at-rate processing of high speed serial data for optical communication applications, implemented in the IBM 8HP SiGe BiCMOS technology. Specifically, the authors describe a 16:1 multiplexer and a 1:16 demultiplexer, each assembled into a package designed to support 80 Gbps data rates. The maximum speed of the packaged components (multiplexer: 70 Gbps, demultiplexer: 60 Gbps) is among the highest reported to date for this generation SiGe technology, particularly for circuits with this level of complexity (>10,000 transistors)

HIGH-SPEED, LOW-POWER DIGITAL AND ANALOG CIRCUITS IMPLEMENTED IN IBM SiGe BiCMOS TECHNOLOGY

Under the auspices of Defense Advanced Research Project Agencys Microsystems Technology Office (DARPA/MTO) Low Power Electronics Program, the Mayo Foundation Special Purpose Processor Development Group is exploring ways to reduce circuit power consumption, while maintaining or increasing functionality, for existing military systems. Applications presently being studied include all-digital radar receivers, electronic warfare receivers, and other types of digital signal processors. One of the integrated circuit technologies currently under investigation to support such military systems is the IBM Corporation silicon germanium (SiGe) BiCMOS process. In this paper, design methodology, simulations and test results from demonstration circuits developed for these applications and implemented in the IBM SiGe BiCMOS 5HP (50 GHz fT HBTs with 0.5 μm CMOS) and 7HP (120 GHz fT HBTs with 0.18 μm CMOS) technologies will be presented.

Interconnect Analysis for 80-Gbps Serial Link Design

This paper presents a case study of the modeling and simulation methods used to design the signal path for a proposed 80-Gbps serial data link between digital systems. This design includes flip-chip transitions from custom IBM 8HP integrated circuits to multilayer organic substrates, with coaxial-cable connections between substrates. Discussion topics include interconnect material selection, detailed 3-D electromagnetic modeling of the conductor transitions and signal paths, time-domain circuit simulation of the complete data path including the driver and receiver, and bit-error rate analysis of the complete link. Simulated data are presented.