Daniel J. Schwab

A 20 GS/s 5-Bit SiGe BiCMOS Dual-Nyquist Flash ADC With Sampling Capability up to 35 GS/s Featuring Offset Corrected Exclusive-Or Comparators

The design and wafer probe test results of a 5-bit SiGe flash ADC are presented. The integrated circuit, fabricated in a 200/250 GHz fT/Fmax, SiGe BiCMOS technology, provides a 5-bit analog to digital conversion with dual Nyquist operation at sample frequencies up to 20 GHz. Sampling clock rates are demonstrated as high as 35 GS/s. The ADC makes use of a comparator with an integrated exclusive-or function to reduce power consumption. The device also generates two half-rate interleaved outputs to ease data capture with laboratory equipment. An effective number of bits (ENOB) of nearly 5.0 is achieved for low-frequency input tones, dropping to 4.0 at 10 GHz.

A 35 GS/s 5-Bit SiGe BiCMOS flash ADC with offset corrected exclusive-or comparator

The design and wafer probe test results of a 5-bit SiGe ADC are presented. The integrated circuit, fabricated in a 200/250 GHz fT/Fmax, SiGe BiCMOS technology, provides a 5-bit analog to digital conversion with input tone frequencies up to 20 GHz and sampling clock rates up to 35 GS/s. The ADC makes use of a comparator with an integrated exclusive-or function to reduce power consumption. The device also generates two half-rate interleaved outputs to ease in data capturing with laboratory equipment. An effective number of bits (ENOB) of nearly 5.0 is achieved for low frequency input tones, dropping to 4.0 at 10 GHz.

Design of a Compact System Using a MEMS Accelerometer to Measure Body Posture and Ambulation

Interest in studying human posture, movement, and physical activity is growing due in part to the increasing prevalence of obesity. Accelerometers are commonly used in motion analysis systems to enable researchers to conduct studies outside of the traditional laboratory environment; however the available systems tend to be bulky and unsuitable for long-term studies. Therefore, a need exists for a physically robust, yet compact motion analysis system that can be easily worn for an extended time period without disrupting the persons range of motion. Here we describe our on-going efforts to develop a robust, compact system that can measure body posture and movement using a tri-axial accelerometer, and then store this data on a secure digital memory card. This device can be easily configured to collect accelerometer data for specific applications in human motion analysis. In the future, this device will be used to study physical activity in free-living individuals

Emerging multigigahertz digital and mixed-signal integrated circuits targeted for military applications: dependence on advanced electronic packaging to achieve full performance

A revolution is occurring in several device and integrated circuit technologies (silicon CMOS and its extensions such as silicon germanium and silicon on insulator [SOI] and the so-called III-V compound semiconductors including indium phosphide and gallium arsenide), as well as in solid-state sensors such as infrared detectors enabled by the new materials and devices. These new components are being used to enhance the performance of many systems, and even to create systems never before available, of present interest to the U.S. Department of Defense and of likely near-term interest to parts of the commercial electronics industry such as the landline, wireless, and satellite telecommunications industry. These new components require advanced electronic packaging that does not restrict or degrade their performance. Unfortunately largely due to commercial cost pressures, research in and small-lot manufacture of high-performance packaging though still feasible and not lacking for good ideas for possible enhancement, are no longer being actively pursued either by the principal U.S. government agencies (e.g., DARPA, Air Force), by the commercial electronic packaging industry, or by commercial consortia such as the Microelectronics and Computer Technology Corporation (defunct as of June 2000), Semiconductor Research Corporation (SRC), or Sematech Inc. This paper discusses recent examples of high-performance components and integrated circuit technologies and describes how they are being exploited in new or upgraded systems. Advances in packaging technology that will be required to support the new integrated circuits are also described. In conclusion, several possible approaches are reviewed by which the United States can regain momentum in the development of performance-driven packaging technologies.

Design of Posture and Activity Detector (PAD)

In recent years, there has been much research and development of wearable devices using accelerometers for studying physical activity. Previously, we have described the development of the Posture and Activity Detector (PAD). After demonstrating success with PAD, we were motivated to improve the design by taking the device one step further and implementing all of these components on a single printed circuit board, adding a few additional features to make the system more flexible, and custom-designing an outer case. We have continued our efforts in improving PAD with respect to software development as well as making PAD more physically robust and mass producible. In this paper, the specifications for PAD will be outlined including its hardware and software components, and clinical research applications.

Implementation of a gallium arsenide multichip digital circuit operating at 500-1000 MHz clock rates using a Si/Cu/SiO/sub 2/ MCM-D technology

Two different deposited multichip modules (MCMs) were fabricated in nCHIPs nC3000 Si/Cu/SiO/sub 2/ process. The first of these MCMs was a passive test coupon containing a variety of microstrip and stripline transmission line structures, allowing the measurement of dc and ac signal amplitude losses in long conductors, as well as assessments of crosstalk and reflections as functions of line dimensions and spacings. The second MCM incorporated sixteen Gallium Arsenide (GaAs) integrated circuits, all designed to work together at clock rates in the hundreds of MHz; all components were attached, face up, with an aluminum wire bonding process. The design, fabrication, assembly and test processes for these modules will be described, as well as the lessons learned about this MCM process for the design of subsystems up to the high hundreds of MHz clock rates.

A chips-first multichip module implementation of passive and active test coupons utilizing Texas Instruments' high density interconnect technology

In this paper, we describe the development and measurement of two separate test structures, or coupons to assess the performance of Texas Instruments chips-first multichip module technology at high operating clock rates, A passive coupon containing a variety of microstrip and stripline transmission line structures allowed the measurement of DC and AC signal amplitude losses in long conductors, as well as assessments of crosstalk and reflections as functions of line dimensions and spacings. An active coupon containing 16 interconnected gallium arsenide (GaAs) chips of two separate designs allowed the assessment of this MCM technologys ability to support the propagation of digital signals at clock and pulse rates above 500 MHz, and the ability of the power and ground plane structures to deliver clean power to the operating components. These comprehensive tests have allowed the development of design rules for developing future high performance systems using this unique packaging technology. Finally, comments are presented regarding future directions for this technology to lower manufacturing costs while preserving the high levels of operational performance demonstrated by these tests.

Implementation of digital circuits in an InP scaled HBT technology

The Mayo Foundation Special Purpose Processor Development Group (Mayo) and HRL Laboratories (HRL) are developing circuits for implementation in an indium phosphide (InP) scaled heterojunction bipolar transistor (HBT) technology which has the potential for very high performance analog and digital operation. Preliminary results from HRL show that the f/sub T/ of the devices can be improved from 90 GHz for the HRL InP standard (2 micron emitter) HBT technology to approximately 180 GHz for this scaled (1 micron emitter) HBT technology. Mayo has designed several digital circuits in this scaled technology, the initial test results for which are reported in this paper.

Application of a 3000-gate GaAs array in the development of a gigahertz digital test system

The characterization of a high-speed GaAs LSi gate array and its personalization as the central control chip for a gigahertz-rate digital test system are described. The array is a 1020-configurable-cell, 3000-gate device that utilizes a commercially available enhancement/depletion (E/D) mode IC process. The development and experimental evaluation of an array personalization designed to characterize all logic macros, the array speed-power performance, and a simple MSI arithmetic element are described. The results of the evaluation of this first design were used to design a digital tester control chip for use at clock rates of up to 1 GHz. Issues in the design of a digital tester are outlined, and the architectural features of a modular tester providing synchronous data acquisition, high-speed RAM control, and pattern generation are discussed. >