Erik Schüler
Universidade Federal do Rio Grande do Sul
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Publication
Featured researches published by Erik Schüler.
symposium on integrated circuits and systems design | 2005
Carlos Arthur Lang Lisbôa; Erik Schüler; Luigi Carro
Future technologies will present devices so small that they will be heavily influenced by electromagnetic noise and SEU induced errors. Since many soft errors might appear at the same time, classical fault tolerance techniques, such as TMR, will no longer provide reliable protection and will make new design approaches necessary. This study shows that the TMR approach has intrinsic weaknesses that impair its effectiveness in the presence of multiple faults, and proposes a new technique that provides better protection than TMR for single as well as multiple faults. The proposed technique is based on the use of some analog components among the digital circuits. We present results based on a multiplier, and show that the technique is scalable to withstand higher quantities of simultaneous faults.
defect and fault tolerance in vlsi and nanotechnology systems | 2005
Erik Schüler; Luigi Carro
As the transistor gate length goes straightforward to the sub-micron dimension, the possibilities of occurrence of external interferences in these devices also increase. Moreover, the process variability further degrade this scenario. The direct effect of such external and/or intrinsic interferences is, in many cases, the total mismatch between the desired answer of the system and the achieved answer resulting from single bit flips. This way, new techniques must be studied in order to guarantee the correct operation of these systems. This work presents the use of a totally digital sigma-delta modulator that is used to develop arithmetic operations, which are further used to develop a FIR filter. Simulations results show that, even with the insertion of a large amount of faults, one can still obtain a nonfaulty behavior in the SNR of complex application.
european test symposium | 2006
Erik Schüler; D. Scain Farenzena; Luigi Carro
As microelectronics evolves smaller into the nanometric scale, external interferences starts to be harmful to the system expected behavior. As classical systems do not handle adequately faults caused by such sources, new topologies are proposed. Our present work proposes a solution for this problem consisting on the use of sigma-delta modulation in order to obtain a fault-tolerance even in presence of multiple faults. This paper provides the mathematical analysis and demonstration to support the proposed approach
defect and fault tolerance in vlsi and nanotechnology systems | 2007
Erik Schüler; A.A. de Souza; Luigi Carro
Spare parts technique has been widely used in digital designs. As memory cells are more susceptible to defects and faults than logic cells, redundancy has been extensively used for enhancing defect and fault tolerance through repair by spare replacement. The technique also aims yield increase, and points to be a very good solution since density integration gets ever higher. In this work, we propose the use of spare parts to develop reliable analog circuits, thus increasing fault tolerance by choosing among many identical blocks, the best ones that will compose the circuit. An example using a mixed-signal FIR filter is presented, showing that the technique can easily be adapted to help increase yield of analog circuits, too.
Journal of Electronic Testing | 2007
Erik Schüler; Marcelo Ienczczak Erigson; Luigi Carro
The occurrence of soft-faults in digital circuits due to single event upsets (SEU) caused by particle hits has been reported in many works, and it has been claimed that, as the transistor dimensions shrink, multiple and simultaneous faults will be a common scenario in future technologies. Many techniques have been proposed to cope with these kinds of faults, most of them based on hardware or software redundancy. In this work, we present a new paradigm, which is based on signal redundancy, that is, the signal to be processed will contain a certain amount of redundancy, in such a way that, even under the occurrence of multiple faults, the final results will sustain a good resolution for some applications. A DSP microprocessor that uses the technique was prototyped, and some results are presented and compared to typical n-bits binary coded DSP microprocessor architecture, showing the advantages of using the proposed approach.
computational intelligence in bioinformatics and computational biology | 2005
Carla D. Lopes; Erik Schüler; Paulo Martins Engel; Altamiro Amadeu Susin
In this work, a correlation between Event Related Potential (ERP) and visual memory, generally located in occipito-temporal region was found for two classes of subject: a sample with high risk (HR) for alcoholism and a sample of control subjects with low risk (LR). For the ERPs of matching stimulus we describe an application of an artificial neural network (ANN) algorithm proposed by Kohonen and namely Learning Vector Quantization (LVQ) for the classification of ERPs signals from individuals at HR and LR for alcoholism. After training, the LVQs nets were able to correctly classify about 80% of the HR and LR class of ERP. The results of this study suggest, as well, that the reduced amplitude of the c247 and P3 to matching stimuli appears to characterize subjects at HR for alcoholism.
symposium on integrated circuits and systems design | 2003
Marcelo Negreiros; Erik Schüler; Luigi Carro; Altamiro Amadeu Susin
The focus of this work is the testing of RF signal paths, specially mixers. The presented technique is based on spectral analysis and subsampling. It enables the partitioning of the RF signal path, making it easier to locate faulty stages. A synchronization scheme is proposed in order to enable the direct sampling of the high frequency signal, thus avoiding the use of an extra anti-alias filter. Furthermore, as the technique is done mainly digitally, it is suitable to be implemented by a common external digital tester, or even in a BIST scheme for an SoC environment. Theoretical background and experimental results are provided in order to evaluate the feasibility of the method.
Archive | 2007
Marcelo Lubaszewski; Tiago R. Balen; Erik Schüler; Luigi Carro; J.L. Huertas
Radiation effects translated into Single Event Transients (SETs) and Single Event Upsets (SEUs) are dealt with, in this chapter, in the realm of analog and mixed-signal circuits. First of all, we revisit concepts and methods of the analog testing field looking for techniques that may help mitigating, at the system level, SETs and SEUs in these circuits. Then, two mixed-signal case studies are presented. The first case study investigates the effects of SEUs in a new kind of analog circuit: the Field Programmable Analog Arrays (FPAAs). Some FPAA devices are based on SRAM memory cells to implement the user programmability. For this reason the effect of radiation in such circuits can be as dangerous as it is for FPGAs. BIT-flip experiments are performed in a commercial FPAA, and the obtained results show that a single BIT inversion can result in a very different configuration of that previously programmed into the device. The second case study is focused on Σ∆ A/D Converters. A MatLab-based model of such converter is built and a series of fault injection experiments is performed. The results show that the Σ∆ converter can be used in radiation environment, if its digital part is protected. Such protection can be achieved by adopting some design directives. This chapter ends by proposing the use of online analog test methods, in particular self-checking circuits, that can be applied to detect SET and SEU faults during the circuit operation, therefore allowing the design of self-recovering systems. State-of-the-art integrated circuits (with growing functionality, signal heterogeneity, lower dimensions, higher performances, less power consumption) are becoming widely used in space environment in order to meet spacecraft requirements such as
international parallel and distributed processing symposium | 2006
Erik Schüler; Luigi Carro
The use of programmability in systems-on-chip (SoC) brings as the main advantage the possibility of reducing the time-to-market and the cost of design, specially when different systems and functions must cover different markets, going from low-power and low-frequency instrumentation to high frequency communication. This paper presents a technique that can be used to increase the analog programmability in a SoC, also allowing one to integrate more analog functions, while guaranteeing the use of the analog part in a larger range of applications. Practical results are presented showing that the proposed technique can be used from DC to RF applications
symposium on integrated circuits and systems design | 2003
Marcelo Negreiros; Erik Schüler; Luigi Carro; Altamiro Amadeu Susin