Werner Pamler

Diffusion of Sr, Bi, and Ta in amorphous SiO2

Abstract Diffusion of Sr, Bi, and Ta in SiO2 was studied to determine diffusion coefficients and diffusion mechanisms of these elements in the amorphous material. Technological motivation is the introduction of strontium bismuth tantalate (SBT) as ferroelectric material for nonvolatile memories. Diffusion from an SBT layer into a thin layer of SiO2 was promoted by annealing at 800°C for times ranging from 1 to 24 h . Concentration profiles of the diffusing elements in the SiO2 layer were recorded by secondary ion mass spectroscopy (SIMS). The measured profiles were compared to profiles derived from calculations for different diffusion mechanisms. The theoretical profile best matching the form of the measured profile was fitted to the experimental data, yielding information about the diffusion mechanism and the diffusion coefficient. The diffusion coefficient of Sr is in the range of 10 −15 cm 2 / s at 800°C and 10 −14 cm 2 / s for Bi. It was found out that Sr and Bi react with vacancies in the SiO2, forming fast-moving complexes. Tantalum shows no measurable diffusion in this time and temperature range. No information is available about the exact nature of the different Sr and Bi species, since SIMS can only detect elements but not their binding situation. Only indirect indications lead to the theory that vacancies play a role in the transformation from slow- to fast-moving species. Theoretical calculations of the behavior of the elements in SiO2 may help to solve this problem.

Influence of Silicon on Insulator Wafer Stress Properties on Placement Accuracy of Stencil Masks.

The issue of placement control is one of the key challenges of stencil mask technology. A high placement accuracy can only be achieved with a precise control of mechanical stress on a global and local scale. For this reason, the stress properties of the mask blank material -typically silicon on insulator (SOI) wafers- have to be known and adjusted properly. A systematic investigation of initial stress properties of various SOI materials is presented. The study covers bonded and non-bonded wafers and demonstrates a global membrane stress accuracy of 0.1 MPa. Initial SOI-stress properties on a global and local scale are discussed. With the precise control of layer stress and pattern correction methods based on finite-element calculations, a placement accuracy of 12 nm (3σ) is achieved. A sample-to-sample error of 12 nm (3σ) indicates the high stress-uniformity of non-bonded material.

A novel low-temperature (Ba,Sr)TiO 3 (BST) process with Ti/TiN barrier for Gbit DRAM applications

Abstract A new, low temperature (Ba,Sr)TiO 3 (BST) MOCVD process has been established at 580°C deposition temperature which can be used for Gbit DRAM applications using Ti TiN as barrier material. The process window for BST deposition was investigated in terms of deposition temperature, stoichiometry, film thickness, post annealing treatment and variation of the underlying electrode/barrier layer. Electrical characterization revealed specific capacitance values of 45 fF/μm 2 for 25 –30 nm film thickness and 75 fF/μm 2 for 10 nm film thickness which is close to the target value for GBit of 80 – 100 fF/μm 2 . Oxidation resistance of the Ti TiN barrier could be shown up to 600°C. Feasibility of this low temperature BST process has been successfully demonstrated using a 4 Mbit test vehicle.

Platinum contamination issues in ferroelectric memories

The contamination risk of processing with platinum electrodes on device performance in ferroelectric memories is assessed in this work. Details of platinum diffusion to the active regions at annealing temperatures of 800 °C are investigated by secondary ion mass spectroscopy, deep level transient spectroscopy, and Rutherford backscattering spectrometry techniques. Cross sectional transmission electron microscopy and local elemental analysis by energy dispersive x-ray spectroscopy were used to examine the precipitation of Pt in defect free silicon as an eventual cause of gate oxide degradation. The impact of platinum contamination on device performance is evaluated under the typical ferroelectric memory processing conditions. Results from leakage current and charge to breakdown measurements of intentionally contaminated diode and metal–oxide–semiconductor (MOS) structures, respectively, are presented. The results show that the degradation depends strongly on device design and configuration. A phosphorus do...

Impact of platinum contamination on ferroelectric memories

Abstract The impact of platinum contamination on the breakdown properties of gate oxide is reported. Wafers were intentionally contaminated with 1×1013 to 4×1014 at/cm2 Pt after a 7.5 nm gate oxide growth, 300 nm poly-silicon deposition and subsequent phosphorus doping. Breakdown characteristics were evaluated using a voltage ramp method. The current-voltage curves of MOS capacitors show very few low field breakdown events, and the main field breakdown occurs at 12 MV/cm. If compared to clean wafers, platinum does not increase the defect density seriously. It is found from the E-Ramp results that platinum contamination up to 4×1014 at/cm2 does not have a pronounced effect on the gate oxide integrity if the contamination occurs after front-end-of-line processing of device fabrication.

Scaling of Metal Interconnects: Challenges to Functionality and Reliability

Copper‐based nano interconnects featuring CDs well beyond today’s chip generations and air gap structures were fabricated and subjected to electrical characterization and tests to get already today insight on functionality and reliability aspects of metallization schemes in future semiconductor products. Size effects observed already in today’s advanced products will definitely limit the resistivity in future interconnects. Copper diffusion barrier layers were scaled down to the 1nm regime of thicknesses without observable degradation effects regarding adhesion properties and functionality. Interconnect reliability was found to decrease with decreasing barrier thickness. Worst results regarding adhesion properties and interconnect reliability were obtained for vanishing barrier thickness which promotes unrestricted mass flow of copper along the interconnect line. Air gaps were developed and characterized as an alternative approach to porous ultra low‐k materials. They allowed the realization of effective ...