Wolfgang Hönlein

Carbon nanotubes in interconnect applications

Carbon nanotubes with their outstanding electrical and mechanical properties are suggested as an interconnect material of the future. In this paper we will introduce nanotubes, compare their electrical properties with equivalent metal wires made of gold and describe our progress in process integration. Multi-walled carbon nanotubes are grown on 6-inch wafers in a batch process. The resulting nanotubes are evaluated with respect to their conductance as single multiwalled nanotubes and in their implementation as interconnects in vias and contact holes.

A novel capacitor technology based on porous silicon

A capacitor based on an electrochemically etched macroporous silicon substrate and a layered dielectric (ONO) is presented. This solid-state technology allows us to realize values of specific capacitance which so far could only be reached by electrolytic capacitors. The dependence of the capacitance on temperature, frequency, applied bias and time of operation is found to be negligible. Due to a low series resistance and a operating temperature of at least 200 °C the device withstands high a.c. currents. Being a silicon chip, the capacitor is fully compatible with todays surface mounted device and multi-chip module technologies.

Ferroelectric strontium bismuth tantalate thin films deposited by metalorganic chemical vapour deposition (MOCVD)

Thin films of Sr 1-x Bi 2+x Ta 2 O 9 (SBT) have been deposited by metalorganic chemical vapor deposition (MOCVD) on 150 mm Si wafers with Pt/Ti electrodes. The choice of Bi precursor significantly affects the process; film homogeneity is significantly improved when using a β-diketonate Bi precursor in combination with compatible Sr and Ta precursors. A highly repeatable process has been developed, with good run-to-run composition and thickness control. Effects of Bi volatility have been investigated in annealing experiments that show the onset of Bi loss at ∼570°C at reduced pressure (1-10 Torr). Film properties relevant to integrated ferroelectric random access (Fe RAMS) memories have also been characterized. Remenant polarizations (2P r ) up to 24 μC cm -2 have been obtained at 5 V, with 90% saturation of 2P r at 1.5 V and a coercive voltage of 0.52 V for a 140 mn film. Electrical leakage current density values were < 2×10 -8 A cm -2 at 1.5 V. Fatigue endurance has been measured to 10 11 cycles with < 10% degradation in switched charge.

A novel low-temperature (Ba,Sr)TiO 3 (BST) process with Ti/TiN barrier for Gbit DRAM applications

Abstract A new, low temperature (Ba,Sr)TiO 3 (BST) MOCVD process has been established at 580°C deposition temperature which can be used for Gbit DRAM applications using Ti TiN as barrier material. The process window for BST deposition was investigated in terms of deposition temperature, stoichiometry, film thickness, post annealing treatment and variation of the underlying electrode/barrier layer. Electrical characterization revealed specific capacitance values of 45 fF/μm 2 for 25 –30 nm film thickness and 75 fF/μm 2 for 10 nm film thickness which is close to the target value for GBit of 80 – 100 fF/μm 2 . Oxidation resistance of the Ti TiN barrier could be shown up to 600°C. Feasibility of this low temperature BST process has been successfully demonstrated using a 4 Mbit test vehicle.

MOCVD of SrBi 2 Ta 2 O 9 for Integrated Ferroelectric Capacitors

SrBi 2 Ta 2 O 9 (SBT) is a promising material for ferroelectric random access memories (FERAMs) because it has high resistance to fatigue and imprint combined with low coercive field. Metalorganic chemical vapor deposition (MOCVD) offers the ability to produce high quality, conformai SBT films for both high and low density memory applications. An MOCVD process based on liquid delivery and flash vaporization has been developed which allows precise delivery of low vapor pressure precursors to the process. Precursor decomposition has been examined over a wide temperature range and the effects of process pressure have been examined. It is shown that Bi(thdb is superior to Bi(Ph) 3 as a source of Bi, offering a wide decomposition window with compatible Sr and Ta precursors so that a simple, well-controlled, and repeatable process is achieved at low temperatures. Films with 90% conformallity have been grown on 0.6 μm structures with a 1:1 aspect ratio. The MOCVD process yields the fluorite phase, which is transformed to the ferroelectric layered perovskite phase upon annealing in oxygen. Dielectric constants (e) of 200 and remanent polarization (2P r )up to 16 μC/cm 2 have been achieved on 150 mm wafers.

Technology challenges and solutions for 1Gbit and beyond

Abstract The need for higher DRAM densities, for cost effective manufacturing and the price pressure puts the DRAM development on a highly innovative path. The fast pace with which DRAM cell sizes are reduced results in many technology issues. This talk discusses the deep trench cell architecture, its advantages and the main technology innovations that have made the aggressive scaling of the DRAM cell possible. The issues related to Gbit DRAMs, the new challenges and potential innovations will be presented.

Template grown multiwall carbon nanotubes

A range of pure metal and metal compound catalysts have been investigated for chemical vapor deposition (CVD) growth of multi-walled carbon nanotubes on silicon oxide substrates under various conditions. Catalysts including iron, cobalt and nickel and their carbonyl, chloride, oxalate and acetylacetonate compounds deposited on SiO2 substrates were prepared and reduced in flowing hydrogen prior to nanotube growth from hydrogen and acetylene at temperatures ranging from 500 to 750 °C. The highest quality nanotubes were grown from elemental iron and iron compound catalysts at temperatures around 700 °C.

CVD‐Growth of In‐Situ Contacted Single‐Walled Carbon Nanotubes

We report on the CVD‐growth of single‐walled carbon nanotubes (SWCNTs) and their electrical characterization. Growth between catalyst covered Mo‐pads yields in‐situ contacted SWCNTs. With this approach, only one level of conventional photolithography is required to obtain SWCNTs ready for field‐effect measurements. The SWCNT yield depends strongly on the catalyst composition and growth conditions, which have been investigated over a wide range. The growth of isolated SWCNTs in lithographically defined holes is also demonstrated. This is the first step towards the realization of surrounding gate vertical SWCNT field‐effect transistors (VCNTFET), which are expected to outperform future silicon‐based devices.

Controlled CVD‐growth of multiwalled CNTs

Many applications of carbon nanotubes (CNTs) require a material with defined properties, however most synthesis routes yield CNTs of varying purity, structure, diameter, and length. Chemical vapor deposition (CVD) allows a good control over the CNTs synthesis and leads to promising results, however the effect of many parameters remains unclear. In order to improve this situation a comprehensive study was carried out under highly controlled conditions. The used CVD reactor was capable to perform deposition processes with temperature deviations smaller than 1°K. The substrates were patterned Fe films with a thickness below 10 nm on silicon/siliconoxide. The effects of the conditioning of the catalyst prior to growth, growth temperature, and growth time were investigated. The synthesis in a hydrogen/acetylene atmosphere yielded pure multi‐walled CNTs with diameters between 10 – 20 nm. The length of the CNTs was accurately controlled by the growth time. The density of the CNTs can be varied by the preconditio...

Scaling of Metal Interconnects: Challenges to Functionality and Reliability

Copper‐based nano interconnects featuring CDs well beyond today’s chip generations and air gap structures were fabricated and subjected to electrical characterization and tests to get already today insight on functionality and reliability aspects of metallization schemes in future semiconductor products. Size effects observed already in today’s advanced products will definitely limit the resistivity in future interconnects. Copper diffusion barrier layers were scaled down to the 1nm regime of thicknesses without observable degradation effects regarding adhesion properties and functionality. Interconnect reliability was found to decrease with decreasing barrier thickness. Worst results regarding adhesion properties and interconnect reliability were obtained for vanishing barrier thickness which promotes unrestricted mass flow of copper along the interconnect line. Air gaps were developed and characterized as an alternative approach to porous ultra low‐k materials. They allowed the realization of effective ...