Eui-Young Jeong

Analytic Model of S/D Series Resistance in Trigate FinFETs With Polygonal Epitaxy

In this paper, a simple but accurate model is presented to analyze source/drain (S/D) series resistance in trigate fin field-effect transistors, particularly on triangular or pentagonal rather than rectangular epitaxy. The model includes the contribution of spreading, sheet, and contact resistances. Although the spreading and sheet resistances are evaluated modifying standard models, the contact resistance is newly modeled using equivalent models of lossy transmission lines and transformations of 3-D to 2-D geometry. Compared with series resistance extracted from 3-D numerical simulations, the model shows excellent agreement, even when the S/D geometry, silicide contact resistivity, and S/D doping concentration are varied. We find that the series resistance is influenced more by contact surface area than by carrier path from the S/D extension to the silicide contact. To meet the series resistance targeted in the semiconductor roadmap, both materials and geometry will need to be optimized, i.e., lowering the silicide contact resistivity and keeping high doping concentration as well as maximizing the contact surface area, respectively.

Device Design Guidelines for Nanoscale FinFETs in RF/Analog Applications

This letter proposes simple guidelines to design nanoscale fin-based multigate field-effect transistors (FinFETs) for radio frequency (RF)/analog applications in terms of fin height and fin spacing. Geometry-dependent capacitive and resistive parasitics are evaluated using analytic models and are included in a small-signal circuit. It is found that reducing the fin-spacing-to-fin-height ratio of FinFETs, as long as it is compatible with the process integration, is desirable for improving RF performance. This is because the current-gain cutoff frequency and the maximum oscillation frequency are affected by decreasing parasitic capacitance more than by increasing series resistance.

Analysis of Abnormal Upturns in Capacitance–Voltage Characteristics for MOS Devices With High-

In this letter, we analyze the nonsaturating upturns of capacitance under strong accumulation bias in MOS capacitors with high-k dielectrics. By comparing the electrical properties of dielectric samples with and without HfO2 and by varying the ambient temperature, it is found that the conduction through the shallow trap levels in the HfO2 bulk produces not only a steady-state current but also a dynamic current, which, in turn, causes the upturn in capacitance. The addition of RC shunts to the conventional small-signal model is proposed to consider the dynamic leakage effect. The models effectiveness is verified by fitting the measured impedance spectrum and the measured capacitance. We suggest that measuring at a high frequency of hundreds of megahertz eliminates the dynamic interaction by shallow trap levels, allowing gate capacitance to be successfully reconstructed.

k

We quantitatively compared the parasitic capacitance of the planar FETs and the DG FinFETs. Optimization with a fixed Sfin-to-H_fin ratio significantly reduces C_para/W, which renders DG FinFETs comparable to planar FETs. Process variation on W_fin and H_fin should be controlled, otherwise, the C_para uniformity will be worse for DG FinFETs than it is planar FETs.

Dielectrics

DC/AC characteristics of Si bulk FinFETs including middle-of-line levels are precisely investigated using well-calibrated 3-D device simulations for system-on-chip applications. Scaling the fin widths down to 5 nm effectively enhances gate-to-channel controllability and improves RC delay, but a dramatic increase in band-to-band tunneling currents from source-to-drain does not satisfy low-power application in the 7-nm node. All lightly-doped extension regions as a solution could improve band-to-band tunneling currents and total gate capacitances because of better short-channel immunity and lower parasitic capacitances, respectively. Using systematic TCAD-based RC calculation, we suggest optimized overlap/underlap lengths in the 7-nm node FinFETs to overcome the scaling limitations.

Comparative study of geometry-dependent capacitances of planar FETs and double-gate FinFETs: Optimization and process variation

This work investigates the effect of Hfin on the device and circuit characteristics, and discusses the design aspects for the SoC integration such as 6T-SRAM and 2-stage OPAMPs. Table summarizes the device- and circuit-level assessment using the FinFETs and the planar FETs. Even though the gate control of FinFETs is better than of the planar FETs, further attention should be paid to design Hfin of the FinFETs. SoC blocks such as SRAMs require both high density and low power, so the minimum Lgate will restrict designing Hfin. On the other hand, the analog/RF applications prefer long Lgate to achieve high output resistance for better performance, so we may raise the Hfin without losing the gate control capability. Multiple Hfin design may be good choice for the sub-22-nm SoC integration because Hfin may affect the power, density, and the design convenience.

Junction Design Strategy for Si Bulk FinFETs for System-on-Chip Applications Down to the 7-nm Node

The MutS2 homologues have received attention because of their unusual activities that differ from those of MutS. In this work, we report on the functional characteristics and conformational diversities of Thermotoga maritima MutS2 (TmMutS2). Various biochemical features of the protein were demonstrated via diverse techniques such as scanning probe microscopy (SPM), ATPase assays, analytical ultracentrifugation, DNA binding assays, size chromatography, and limited proteolytic analysis. Dimeric TmMutS2 showed the temperature-dependent ATPase activity. The non-specific nicking endonuclease activities of TmMutS2 were inactivated in the presence of nonhydrolytic ATP (ADPnP) and enhanced by the addition of TmMutL. In addition, TmMutS2 suppressed the TmRecA-mediated DNA strand exchange reaction in a TmMutL-dependent manner. We also demonstrated that small-angle X-ray scattering (SAXS) analysis of dimeric TmMutS2 exhibited nucleotide- and DNA-dependent conformational transitions. Particularly, TmMutS2-ADPnP showed the most compressed form rather than apo-TmMutS2 and the TmMutS2-ADP complex, in accordance with the results of biochemical assays. In the case of the DNA-binding complexes, the stretched conformation appeared in the TmMutS2-four-way junction (FWJ)-DNA complex. Convergences of biochemical- and SAXS analysis provided abundant information for TmMutS2 and clarified ambiguous experimental results.

Effect of fin height of tapered FinFETs on the sub-22-nm System on Chip (SoC) application using TCAD simulation

The conventional source/drain series resistance (<i>R</i>_sd) extraction method is not applicable to nanowire field effect transistors (NWFETs), as NWFETs have fluctuating characteristics in <i>Id</i> and there is insufficient physical modeling. In this letter, we propose a modified <i>R</i>_sd extraction method that uses an optimized <i>Id</i> equation and a threshold voltage (<i>V</i>_th) extraction procedure for NWFETs. The <i>Id</i> equation is modified for the geometry of the NWFET, and <i>V</i>_th is obtained from the linear Y-function that can be observed in NWFETs because of volume inversion. A necessary assumption for this procedure is experimentally confirmed using the Y-function, and equations that fit the measured data perform well; this justifies the validity of applying the modified <i>Id</i> equations to NWFETs. Therefore, <i>R</i>_sd is perfectly extracted in all NWFETs and it is observed to be dependent on the channel diameter (<i>d</i>_NW) when normalized by <i>d</i>_NW, indicating that the extension resistance is the dominant component in the total <i>R</i>_sd.

Characterization of multi-functional properties and conformational analysis of MutS2 from Thermotoga maritima MSB8.

In this paper, we propose an optimized design for Si-nanowire FETs in terms of spacer dielectric constant (κsp), extension length (LEXT), nanowire diameter (Dnw), and operation voltage (VDD) for the sub-10 nm technology node. Using well-calibrated TCAD simulations and analytic RC models, we have quantitatively evaluated geometry-dependent parasitic series resistances (RSD) and capacitances (Cpara). Compared with low-κ spacers, high-κ spacers exhibit a higher on/off-current ratio with a lower RSD, but show severe degradation in their AC performance owing to a higher Cpara. Considering the trade-off between RSD and Cpara, optimal geometry-dependent κsp values at various supply voltages (VDD) are determined using gate delay (CV/I) and current-gain cutoff frequency (fT). We found that as LEXT and VDD decrease and Dnw increases, the optimal κsp value shifts from the high-κ to low-κ regime.

Simple S/D Series Resistance Extraction Method Optimized for Nanowire FETs

In this brief, we systematically investigated the effects of fin pitch (FP) and fin height (Hfin) on parasitic resistances and capacitances to achieve the best RC delay, which is an adequate metric of the ac behavior of FinFETs, for Si bulk n/pFinFETs in system-on-a-chip applications. The RC delays were directly extracted from the fully calibrated technology computer aided design I-V/C-V simulation results and quantitatively analyzed using parasitic capacitance components, including a middle-of-the line configuration up to Metal 1. When FP increased, the RC delay likewise increased due to greater Cgg. On the other hand, the RC delay mostly decreased due to greater ON-current as the Hfin increased. The RC delay with different power supply voltages (VDD = 0.55 and 0.75 V) was also studied to see the effect of VDD scaling. Finally, a selective deposition was suggested to improve the RC delay about 13%.