Chang-Woo Sohn

Study on a Scaling Length Model for Tapered Tri-Gate FinFET Based on 3-D Simulation and Analytical Analysis

A compact scaling length model for tapered Tri-gate fin field-effect transistors (FinFETs) is presented based on a 3-D simulation and an analytic potential model. Short-channel effects (SCEs) of rectangular FinFETs can be controlled by designing the fin width, fin height, and gate length to satisfy scaling theory. Tapered FinFETs have a fin top width shorter than the fin bottom width, and they show a different dependence of subthreshold behaviors and SCEs compared to rectangular FinFETs. The proposed scaling length model for tapered FinFETs, expressed as a function of fin bottom width, fin height, and tapering angle, is presented based on the 3-D Poissons equation and a non-Cartesian mesh. The dependence of the subthreshold behaviors of tapered FinFETs calculated with the proposed model is compared with that of rectangular FinFETs. We found that longer fin bottom widths and fin heights of tapered FinFETs can be designed by applying the proposed scaling length model for the scaling parameter.

Analytic Model of S/D Series Resistance in Trigate FinFETs With Polygonal Epitaxy

In this paper, a simple but accurate model is presented to analyze source/drain (S/D) series resistance in trigate fin field-effect transistors, particularly on triangular or pentagonal rather than rectangular epitaxy. The model includes the contribution of spreading, sheet, and contact resistances. Although the spreading and sheet resistances are evaluated modifying standard models, the contact resistance is newly modeled using equivalent models of lossy transmission lines and transformations of 3-D to 2-D geometry. Compared with series resistance extracted from 3-D numerical simulations, the model shows excellent agreement, even when the S/D geometry, silicide contact resistivity, and S/D doping concentration are varied. We find that the series resistance is influenced more by contact surface area than by carrier path from the S/D extension to the silicide contact. To meet the series resistance targeted in the semiconductor roadmap, both materials and geometry will need to be optimized, i.e., lowering the silicide contact resistivity and keeping high doping concentration as well as maximizing the contact surface area, respectively.

Analysis of Contact Effects in Inverted-Staggered Organic Thin-Film Transistors Based on Anisotropic Conduction

In this paper, we propose an analytic model for inverted-staggered organic thin-film transistors, and we use the proposed model to investigate the dependence of contact effect on the voltage bias, the film thickness of the organic semiconductor, and the channel length. In our model, the variable-range-hopping transport is adopted for the conduction in the horizontal direction to the semiconductor-insulator interface, and the space-charge-limited conduction is adopted for the conduction in the vertical direction by considering the molecular orientations. Qualitative agreement is obtained between simulation and measurement in the steady-state characteristics. From simulation study, we notice that the contact resistances vary with the source-gate voltage and with the source-drain voltage, the film thickness requires to be optimized to improve the on-current and the linearity in the linear operating regime, and the overlap length between the gate electrode and the source/drain contact needs to be guaranteed for the short-channel devices because it would not be scaled as much as the channel length.

Device Design Guidelines for Nanoscale FinFETs in RF/Analog Applications

This letter proposes simple guidelines to design nanoscale fin-based multigate field-effect transistors (FinFETs) for radio frequency (RF)/analog applications in terms of fin height and fin spacing. Geometry-dependent capacitive and resistive parasitics are evaluated using analytic models and are included in a small-signal circuit. It is found that reducing the fin-spacing-to-fin-height ratio of FinFETs, as long as it is compatible with the process integration, is desirable for improving RF performance. This is because the current-gain cutoff frequency and the maximum oscillation frequency are affected by decreasing parasitic capacitance more than by increasing series resistance.

Analysis of Abnormal Upturns in Capacitance–Voltage Characteristics for MOS Devices With High-

In this letter, we analyze the nonsaturating upturns of capacitance under strong accumulation bias in MOS capacitors with high-k dielectrics. By comparing the electrical properties of dielectric samples with and without HfO2 and by varying the ambient temperature, it is found that the conduction through the shallow trap levels in the HfO2 bulk produces not only a steady-state current but also a dynamic current, which, in turn, causes the upturn in capacitance. The addition of RC shunts to the conventional small-signal model is proposed to consider the dynamic leakage effect. The models effectiveness is verified by fitting the measured impedance spectrum and the measured capacitance. We suggest that measuring at a high frequency of hundreds of megahertz eliminates the dynamic interaction by shallow trap levels, allowing gate capacitance to be successfully reconstructed.

k

For the higher degree of integration and better performance of a device, the feature size of conventional MOSFET is expected to go down under 20 nm within a few years [1] and the nanowire FET (NWFET) is the most conspicuous candidate for the future device application. However, in the case of conventional inversion mode NWFETs (cINT), the formation of an abrupt junction for the source/drain (SD) is one of the technical obstacles [2]. Recently, junctionless NWFETs (JNT) where the channel and SD region are doped with the same dopant type has been suggested [3]. In this work, the n-type JNTs and cINT are fabricated with the gate length (LG) of 20 ∼ 250 nm and compared their electrical DC characteristics and low-frequency noise characteristics.

Dielectrics

The conventional source/drain series resistance (<i>R</i>_sd) extraction method is not applicable to nanowire field effect transistors (NWFETs), as NWFETs have fluctuating characteristics in <i>Id</i> and there is insufficient physical modeling. In this letter, we propose a modified <i>R</i>_sd extraction method that uses an optimized <i>Id</i> equation and a threshold voltage (<i>V</i>_th) extraction procedure for NWFETs. The <i>Id</i> equation is modified for the geometry of the NWFET, and <i>V</i>_th is obtained from the linear Y-function that can be observed in NWFETs because of volume inversion. A necessary assumption for this procedure is experimentally confirmed using the Y-function, and equations that fit the measured data perform well; this justifies the validity of applying the modified <i>Id</i> equations to NWFETs. Therefore, <i>R</i>_sd is perfectly extracted in all NWFETs and it is observed to be dependent on the channel diameter (<i>d</i>_NW) when normalized by <i>d</i>_NW, indicating that the extension resistance is the dominant component in the total <i>R</i>_sd.

Comparative study of fabricated junctionless and inversion-mode nanowire FETs

We study quasi-ballistic transport in nanoscale high-κ/metal gate nMOSFETs based on radio-frequency (RF) <i>S</i>-parameter analysis. An RF <i>S</i>-parameter-based simple experimental methodology is used for direct extraction of device parameters (i.e., <i>L</i>_eff, <i>R</i>_sd, and <i>C</i>_inv) and the effective carrier velocity v_eff from the targeted short-channel devices. Furthermore, an analytical top-of-the-barrier model, which self-consistently solves the Schrödinger-Poisson equations, is used to determine the ballistic carrier velocity <i>v</i>_inj at the top of the barrier near the source. Based on the results of the experimental extraction and analytical calculations, backscattering coefficient <i>r</i>_sat and ballistic ratio <i>BR</i>_sat are calculated to assess the degree of the transport ballisticity for nMOSFETs. It is found that conventional high-κ/metal gate nMOSFETs will approach a ballistic limit at an effective gate length <i>L</i>_eff of approximately 7 nm.

Simple S/D Series Resistance Extraction Method Optimized for Nanowire FETs

This paper describes the degradation and recovery characteristics of SiGe pMOSFETs with a high-k/metal gate stack under negative-bias temperature instability (NBTI) stress. The threshold voltage instability (ΔVth) of SiGe pMOSFETs shows an increased percentage of recovery (R) as well as lower degradation than those of control Si pMOSFETs. It is found that the recovery characteristics of SiGe and Si pMOSFETs have similar dependencies on various stress conditions, and the increased R of SiGe pMOSFETs is mainly attributed to their lower degradation characteristic. Under real operating conditions, most of the ΔVth caused by hole trapping would be rapidly recovered through a fast recovery process, and newly-generated interface traps during the stress would determine the degradation level of Vth. The SiGe pMOSFETs show lower stress-induced interface traps; thus, they would display more reliable NBTI characteristics than Si pMOSFETs under real operating conditions.

Comprehensive Study of Quasi-Ballistic Transport in High-

Quasi-ballistic transport in nanoscale high-k/metal gate nMOSFETs is investigated by RF S-parameter analysis. A simple experimental method based on RF S-parameter is used for direct extraction of device parameters (Leff, Cgc, RSD) and the effective carrier velocity (veff) from targeted short channel devices. The ballistic carrier velocity (vinj) at the top of the barrier near the source is determined by using the top-of-the-barrier model which self-consistently solves Schrödinger-Poisson equations. Combining the experimental extraction and the analytical top-of-the-barrier model, the backscattering coefficient (rsat) is calculated to assess the degree of the transport ballisticity for the high-k/metal gate nMOSFETs.