Ye-Ram Kim

Analytic Model of S/D Series Resistance in Trigate FinFETs With Polygonal Epitaxy

In this paper, a simple but accurate model is presented to analyze source/drain (S/D) series resistance in trigate fin field-effect transistors, particularly on triangular or pentagonal rather than rectangular epitaxy. The model includes the contribution of spreading, sheet, and contact resistances. Although the spreading and sheet resistances are evaluated modifying standard models, the contact resistance is newly modeled using equivalent models of lossy transmission lines and transformations of 3-D to 2-D geometry. Compared with series resistance extracted from 3-D numerical simulations, the model shows excellent agreement, even when the S/D geometry, silicide contact resistivity, and S/D doping concentration are varied. We find that the series resistance is influenced more by contact surface area than by carrier path from the S/D extension to the silicide contact. To meet the series resistance targeted in the semiconductor roadmap, both materials and geometry will need to be optimized, i.e., lowering the silicide contact resistivity and keeping high doping concentration as well as maximizing the contact surface area, respectively.

Junction Design Strategy for Si Bulk FinFETs for System-on-Chip Applications Down to the 7-nm Node

DC/AC characteristics of Si bulk FinFETs including middle-of-line levels are precisely investigated using well-calibrated 3-D device simulations for system-on-chip applications. Scaling the fin widths down to 5 nm effectively enhances gate-to-channel controllability and improves RC delay, but a dramatic increase in band-to-band tunneling currents from source-to-drain does not satisfy low-power application in the 7-nm node. All lightly-doped extension regions as a solution could improve band-to-band tunneling currents and total gate capacitances because of better short-channel immunity and lower parasitic capacitances, respectively. Using systematic TCAD-based RC calculation, we suggest optimized overlap/underlap lengths in the 7-nm node FinFETs to overcome the scaling limitations.

Simple S/D Series Resistance Extraction Method Optimized for Nanowire FETs

The conventional source/drain series resistance (<i>R</i>_sd) extraction method is not applicable to nanowire field effect transistors (NWFETs), as NWFETs have fluctuating characteristics in <i>Id</i> and there is insufficient physical modeling. In this letter, we propose a modified <i>R</i>_sd extraction method that uses an optimized <i>Id</i> equation and a threshold voltage (<i>V</i>_th) extraction procedure for NWFETs. The <i>Id</i> equation is modified for the geometry of the NWFET, and <i>V</i>_th is obtained from the linear Y-function that can be observed in NWFETs because of volume inversion. A necessary assumption for this procedure is experimentally confirmed using the Y-function, and equations that fit the measured data perform well; this justifies the validity of applying the modified <i>Id</i> equations to NWFETs. Therefore, <i>R</i>_sd is perfectly extracted in all NWFETs and it is observed to be dependent on the channel diameter (<i>d</i>_NW) when normalized by <i>d</i>_NW, indicating that the extension resistance is the dominant component in the total <i>R</i>_sd.

Impact of the spacer dielectric constant on parasitic RC and design guidelines to optimize DC/AC performance in 10-nm-node Si-nanowire FETs

In this paper, we propose an optimized design for Si-nanowire FETs in terms of spacer dielectric constant (κsp), extension length (LEXT), nanowire diameter (Dnw), and operation voltage (VDD) for the sub-10 nm technology node. Using well-calibrated TCAD simulations and analytic RC models, we have quantitatively evaluated geometry-dependent parasitic series resistances (RSD) and capacitances (Cpara). Compared with low-κ spacers, high-κ spacers exhibit a higher on/off-current ratio with a lower RSD, but show severe degradation in their AC performance owing to a higher Cpara. Considering the trade-off between RSD and Cpara, optimal geometry-dependent κsp values at various supply voltages (VDD) are determined using gate delay (CV/I) and current-gain cutoff frequency (fT). We found that as LEXT and VDD decrease and Dnw increases, the optimal κsp value shifts from the high-κ to low-κ regime.

Investigation of

In this brief, we systematically investigated the effects of fin pitch (FP) and fin height (Hfin) on parasitic resistances and capacitances to achieve the best RC delay, which is an adequate metric of the ac behavior of FinFETs, for Si bulk n/pFinFETs in system-on-a-chip applications. The RC delays were directly extracted from the fully calibrated technology computer aided design I-V/C-V simulation results and quantitatively analyzed using parasitic capacitance components, including a middle-of-the line configuration up to Metal 1. When FP increased, the RC delay likewise increased due to greater Cgg. On the other hand, the RC delay mostly decreased due to greater ON-current as the Hfin increased. The RC delay with different power supply voltages (VDD = 0.55 and 0.75 V) was also studied to see the effect of VDD scaling. Finally, a selective deposition was suggested to improve the RC delay about 13%.

RC

In this paper, we show the junctionless nanowire FETs (JNTs) with gate length of 20 nm and the conventional inversion mode nanowire FETs (cINTs). The fabricated JNT has shown better electrical characteristics with high Ion / Ioff ratio (>106) and subthreshold slope (∼75 mV/dec) than cINT, which means that the simpler fabrication process without junction formation makes the JNT a promising candidate for the next generation CMOS technology node. The nano-scale three dimensional and radial shaped structures lead to more oxide and interface traps and 1-D or 3-D configurations between the channel and source/drain. Consequently, drain current fluctuation, channel and series resistances become dominant parameters in estimating the performance of nanowire FETs (NWFETs) as the channel length is scaled down. Here, we report more reliable extraction of Rsd with other device parameters such as effective mobility, threshold voltage by the Y-function method, and volume trap density by the flicker noise analysis. In addition, radius dependence of flicker noise is discussed.

Parasitics Considering Middle-of-the-Line in Si-Bulk FinFETs for Sub-14-nm Node Logic Applications

The low-frequency noise (LFN) of a p-type nanowire FET (p-NWFET) was characterized and compared with that of an n-type NWFET (n-NWFET) in terms of dominant noise source and its location in the channel region. An inverse proportional dependence of the noise level on channel diameter was observed in the p-NWFET but not in the n-NWFET. The LFN was observed to be mainly generated by Hooge mobility fluctuation in the p-NWFET. Under a switched biasing condition, p-NWFET showed no substantial LFN reduction (in contrast to the n-NWFET), indicating that the carrier number fluctuation was insignificant. This was due to the compressive stress induced by embedded SiGe with heavier transverse effective hole mobility.

Fabrication and characterization of gate-all-around silicon nanowire field effect transistors

Source/drain series resistances (Rsd) of n- and p-type double-gate fin field-effect transistors (FinFETs) were successfully extracted using the methods applicable to short channel devices. Rsd is decomposed into spreading, sheet, and contact resistances considering top and sidewall contact resistances separately. Resistivity parameters defined in the analytic model were extracted from the extracted Rsd values of FinFETs with different fin widths and spacer lengths, and the proposed model showed good agreement to the experimental data.

Investigation of Low-Frequency Noise in p-type Nanowire FETs: Effect of Switched Biasing Condition and Embedded SiGe Layer

Source/Drain series resistance (Rsd) is extracted using methods applicable to short channel nand p-type FinFETs. Rsd is decomposed into spreading, sheet, and contact resistances using the analytic model considering top and sidewall contact resistivity separately. Resistivity parameters in the analytic model were effectively extracted from experimental data, and the Rsd components with different fin widths were investigated.

Extraction of source/drain resistivity parameters optimized for double-gate FinFETs

Series resistance (R<inf>sd</inf>) and mobility attenuation factors (θ<inf>1</inf>, and (θ<inf>2</inf>) of silicon nanowire FET (NWFET) are simultaneously extracted using Tanaka method (YФ method) and Y-function technique. Consecutively, simulated drain current (I<inf>d</inf>) and transconductance (g<inf>m</inf>) is precisely fitted to the measured data with the extracted (θ<inf>1</inf>, (θ<inf>2</inf>, and R<inf>sd</inf>. Significantly reduced mobility degradation due to volume inversion effect makes the Rsd values extracted from both the Y-function technique and the YФ method practically the same. It is quantitatively confirmed that the Y-function technique assuming constant mobility is quite reliable to extract R<inf>sd</inf>. Moreover, the dependence of the R<inf>sd</inf> on the channel diameter (d<inf>nw</inf>) and the doping condition (n-, p-type) is investigated. It is shown that extension resistance (R<inf>ext</inf>) increases as d<inf>nw</inf> decreases and R<inf>sd</inf> of p-type NWFET is smaller than that of n-type NWFET.