Tae-Je Cho

Power Delivery Network Design for 3D SIP Integrated over Silicon Interposer Platform

As mobile hand-held devices including mobile phone are required to provide multi-media services more and more, it is necessary that the various hardware including high speed memory, high capacity data storage device, and high performance logic processor are integrated into the limited volume, which results in high density 3D SIP. In this work, power delivery network for 3D SIP integrated on silicon interposer will be discussed. The silicon interposer used in 3D SIP includes integrated decoupling capacitor, which gives good power delivery performance.

Fine pitch chip interconnection technology for 3D integration

3D-IC packaging using through silicon via technology has been extensively developed to meet small form factor and low power consumption for next generation devices. For 3D chip integration, a robust micro-joining technology is required to stack Si chips, which usually offer high I/O pin counts to achieve better electrical performance. As for the 3D chip stacking methodology, chip-on-wafer bonding is expected to have higher yield than chip-on-chip or wafer-on-wafer bonding. In the case of chip-on-chip bonding, the large amount of bottom chip warpage induced by the printed circuit board during bonding causes a serious drop in the joining yield. Wafer-on-wafer bonding is limited by lower cumulative yield even though the throughput is very high. In this study, the chip-on-wafer bonding method is used for 3D chip stacking, and the 40um pitch interconnection technology is developed. Both fluxless thermo-compression and conventional flip chip bonding technique were adopted and evaluated for chip-on-wafer bonding. By optimizing the bonding conditions, the good bondability and electrical connections were achieved regardless of bonding technique.

Mechanisms of die and underfill cracking in flip chip PBGA package

This paper focuses on understanding the mechanisms of die and underfill cracking during MRT (Moisture Resistance Test, JEDEC level 3) and TCT (Thermal Cycling Test, -55-125/spl deg/C). A parametric study has been performed to understand the influence of die and substrate thickness, and metal attachment on die cracking. It is found that a combination of thinner die and thicker substrate leads to good results. In the case of metal stiffener attachment on die backside using low modulus adhesive, die cracking is eliminated. Underfill cracking can be categorized into three groups, popcorn cracking, corner cracking, and edge cracking. The popcorn and corner cracking originate from interfacial delamination between underfill and die passivation. Such cracking is improved by baking the organic substrate before the underfill process and by using high adhesion strength underfill. Since the mechanism of underfill edge cracking is very complicated, mechanical simulations and experiments are conducted to understand it. The authors conclude that underfill edge cracking is closely related to the local CTE mismatch between underfill material and silicon die, and can be eliminated by using low CTE underfill material and by control of underfill fillet size.

A study on wafer level molding for realizing 3-D integration

3D-IC packaging using through silicon via technology has been extensively developed to meet small form factor and low power consumption demands for next generation devices. A wafer molding technology is required for 3D chip integration. Wafer molding is carried out in the chip-to-wafer process to ensure suitable levels of mechanical strength are reached. The key to wafer level mold processing is the reduction of warpage. This paper discusses the material developments and steps taken for process optimization in the wafer molding process to reduce warpage. A 2 chip stack arrangement was used for this investigation, with a 12 inch bottom wafer containing vias, and 9×9 mm top chip wafers. The evaluation was run systematically in three major phases. In the first phase, the levels of warpage experienced during the packaging processes were simulated. The evaluation of three different types of material (Epoxy, Silicone and Hybrid) was carried out in the second phase. The third and final phase involved the testing for warpage at room and high temperature conditions of the epoxy and hybrid based resins. The silicone based resin was also evaluated with varying amounts of filler and adhesion promoter. The modulus and coefficient of thermal expansion (CTE) were found to be extremely important, since lowering this property would result in low warpage levels, both at room and high temperatures, which control the water absorption and temperature cycle reliability in the silicone based resin were established.

Development of multi stack package with high drop reliability by experimental and numerical methods

Board level drop reliability of MSP (multi stack package) composed of a logic chipset package at bottom and an MCP (multi chip package) at top was investigated. The reliability of the package was tested by a developed drop (shock) tester. Applied shock level was half sine shape with 1500 G peak acceleration and 0.5 msec duration time. Failures were detected by four daisy chain loops going through solder balls and traces on each package. All failures were observed at the bottom chipset solder ball. The locations of failed balls were observed by dye and pry technology. The detailed physics of failure was observed by cross sectioning. EDX analysis was carried out at the failed IMC (inter-metallic compound) layer and brittle fracture between Cu6 Sn5 and Cu3Sn was observed. Fluctuation of the test board was measured by an accelerometer, strain gage, and gap sensor. A modal test was performed to measure the natural frequency of the board. Complex phenomena during the short period of the drop were analyzed by numerical simulation; finite element method. A simplified beam and shell model was adopted to obtain the global motion of the board, and a three-dimensional continuum sub model was adopted for the detail analysis of the ball. Both axial force and bending moment on the solder were good failure parameters. Local stress analysis showed stress concentration at the edge of a solder ball. Modal dynamic analysis gave similar result to real time analysis and its computation time was 1/6 of implicit analysis

A new efficient equivalent circuit extraction method for multi-port high speed package using multi-input multi-output transmission matrix and polynomial curve fitting

Modem high-speed integrated circuits for multi-gigabit applications require high-density packages with several hundred YO pins, which also require a wideband circuit model of package. Since a wideband model of a multi-port network is generally calculated by a full-wave field solver and given in the form of a scattering parameter, a SPICEcompatible circuit model must be extracted from a scattering matrix. We present the concrete maxtrix formulation for tranforming scattering parameter to transmission matrix for a ZN-port network . This transformation results in a new efficient equivalent circuit extraction method, which conveniently incorporates accurate electromagnetic models of an interconnecting structure including electronic package into a circuit simulator. By using this new exfraction method, we can easily determine the valid bandwidth of an equivalent circuit model .

Reliability of flip chip BGA package on organic substrate

In this paper various reliability issues of the flip chip package on organic substrate, such as the 1st level bump joint reliability, die cracking, underfill cracking, and 2nd level solder ball joint reliabilty, are primarily described. This paper discusses the reasons and resolutions of failures.

Low temperature solid-state-diffusion bonding for fine-pitch Cu/Sn/Cu interconnect

3D interconnection is one of the key technologies for futures 3D integration. Cu/Sn/Cu Solid-State-Diffusion (SSD) bonding has been proposed and investigated for fine-pitch interconnection in this paper. Wafer-level bumps, with 20μm-pitch and daisy-chain and Kelvin structures, were pretreated for surface activation and bonded face to face with a wafer bonder. After bonding at 200°C for 1hour, the as-bonded interfacial microstructure is Cu/Cu3Sn/Cu6Sn5/Cu3Sn/Cu, without pure Sn remained. When the bonded wafers were annealed at 200°C for 30min under N2 atmosphere, the Cu6Sn5 was almost exhausted. And the bonding strength increased from 48MPa to 62MPa. The electrical resistance of the daisy chain including 100 bumps is 11.8Ω, which consisting of redistribution layer and bonding bumps. Additionally, the resistance of the Kelvin structure is 15mΩ.The resistance values are approximate to the theory estimation. Bonding pairs after high temperature storage (HTS) at 150°C for 500hrs were checked for reliability study. Kirkendall voids with various dimensions are discussed for both as-bonded and annealing interfaces. It is concluded that Cu/Sn/Cu SSD bonding would be one of the candidates for fine-pitch interconnect.

Design of CMOS voltage controlled oscillators using package inductor

This paper presents three different types of CMOS Voltage-Controlled-Oscillators (VCO) with the integration of embedded inductors in a multi-layer package. A high quality (Q) inductor, pertinent to creating an efficient VCO, is easily made with a thick wiring line in a multi-layer package, The embedded inductors are designed with two different packaging technologies. One is a Fine Pitch Ball Grid Array Packaging (FBGA) technology and the other is a Wafer Level Packaging (WLP) technology. The FBGA inductor showed a Q-factor about 60 at the frequency of 2GHz and that of a WLP inductor was about 25 while at 2GHz. The performances of VCOs using embedded inductors were compared with the control, a VCO designed with conventional on-chip inductors. The use of FBGA and WLP created numerous advantages. The Total Figure-Of-Merit (FOM) was enhanced due to not only reduced phase-noises, but also to improved efficiency and tuning range.

Model-order estimation and reduction of distributed interconnects via improved vector fitting

This paper introduces an automated method estimating and reducing the order of macromodel for fast transient simulation. The proposed method improves the vector fitting algorithm for extracting the reduced-order macromodel from the accurate macromodel having redundant poles and residues. The performance of the proposed method has been demonstrated through several test cases.