Eunseung Jung

Scaling and reliability of NAND flash devices

Numerous scaling limitations of NAND flash memory have arisen due to the intrinsic nature of the operational principle of NAND flash memory and those limitations eventually lead to a paradigm shift in the NAND flash technology from the planar cell to the vertical NAND cell. In this paper, the limitations of scaling which induce the evolution of the NAND cell as well as the current trends of NAND technology are reviewed.

Si FinFET based 10nm technology with multi Vt gate stack for low power and high performance applications

10nm logic technology using Si FinFET is developed for low power and high performance applications. Power-speed gain of 27% compared to 14nm technology node was obtained using four key developments: 1) advanced gate stack engineering enabling 4 multi-Vt devices, 2) 3rd generation Fin technology, 3) highly doped source/drain (S/D), and 4) contact resistance optimization. CVD liner for BEOL process was also applied for better metal fill capability. Finally yield of the smallest ever SRAM with 0.04um2 SRAM bit-cell size was demonstrated.

20nm DRAM: A new beginning of another revolution

For the first time, 20nm DRAM has been developed and fabricated successfully without extreme ultraviolet (EUV) lithography using the honeycomb structure (HCS) and the air-spacer technology. The cell capacitance (Cs) can be increased by 21% at the same cell size using a novel low-cost HCS technology with one argon fluoride immersion (ArF-i) lithography layer. The parasitic bit-line (BL) capacitance is reduced by 34% using an air-spacer technology whose breakdown voltage is 30% better than that of conventional technology.

Verification on the extreme scalability of STT-MRAM without loss of thermal stability below 15 nm MTJ cell

Scalability of interface driven perpendicular magnetic anisotropy (i-PMA) magnetic tunnel junctions (MTJs) has been improved down to 1X node which verifies STT-MRAM for future standalone memory. With developing a novel damage-less MTJ patterning process, robust magnetic and electrical performances of i-PMA MTJ cell down to 15 nm node could be achieved.

Highly functional and reliable 8Mb STT-MRAM embedded in 28nm logic

We fabricated 8Mb 1T-1MTJ STT-MRAM macro embedded in 28nm CMOS logic platform by developing novel integration/stack/patterning technologies. MTJ memory cell array was successfully embedded into Cu backend without open fail and severe degradation of magnetic property. Advanced perpendicular MTJ stack using MgO/CoFeB was developed to show high TMR value of 180% after full integration. In addition, ion beam etching (IBE) process was optimized with power, angle, and pressure to reduce a short fail below 1 ppm. Through these novel technologies, we demonstrated highly functional and reliable 8Mb eMRAM macro having a wide sensing margin and strong retention property of 85 0C and 10yrs.

A novel tensile Si (n) and compressive SiGe (p) dual-channel CMOS FinFET co-integration scheme for 5nm logic applications and beyond

A novel tensile Si (tSi) and compressive SiGe (cSiGe) dual-channel FinFET CMOS co-integration scheme, aimed at logic applications for the 5nm technology node and beyond, is demonstrated for the first time, showing electrical performance benefits and excellent co-integration feasibility. A Strain-Relaxed SiGe Buffer (SRB) layer is introduced as buried stressor and successfully transfers up to ∼1 GPa uniaxial tensile and compressive stress to the Si/SiGe n-/p-channels simultaneously. As the result, both tSi and cSiGe devices show a 40% and 10% electron and hole mobility gain over unstrained Si, respectively. Through a novel gate stack solution including a common interfacial layer (IL), HK, and single metal gate for both n- and pFET, secured process margin for 5nm gate length, low interface trap density (Dit) for SiGe channel and threshold voltage (Vt) target for both the Si and SiGe device are successfully demonstrated. Lastly, reliability investigation shows that tSi and cSiGe, employing the newly developed common gate stack scheme, possess superior reliability characteristics compared with those of equivalent Si devices.

Impact of the crystallization of the high-k dielectric gate oxide on the positive bias temperature instability of the n-channel metal-oxide-semiconductor field emission transistor

The positive bias temperature instability (PBTI) characteristics of the n-channel metal-oxide-semiconductor field emission transistors which had different kinds of high-k dielectric gate oxides were studied with the different stress-relaxation times. The degradation in the threshold voltage followed a power-law on the stress times. In particular, we found that their PBTI behaviors were closely related to the structural phase of the high-k dielectric gate oxide. In an amorphous gate oxide, the negative charges were trapped into the stress-induced defects of which energy level was so deep that the trapped charges were de-trapped slowly. Meanwhile, in a crystalline gate oxide, the negative charges were trapped mostly in the pre-existing defects in the crystallized films during early stage of the stress time and de-trapped quickly due to the shallow energy level of the defects.

Channel Coupling phenomenon as scaling barrier of NAND flash memory beyond 20nm node

A new program disturbance phenomenon appeared from sub 40nm-node NAND flash cell is presented firstly which is named as BTBT Leakage Burst by Channel Coupling (abbr. “Channel Coupling”). With scaling down, the neighboring program channel of 0V grabs strongly the boosted channel at program-inhibited active line not to rise up at the active sidewall and simultaneously, its potential at Si surface is tried to be raised by help of pass voltage. The competition induces the sharp band-bending and thereby sudden enhancement of BTBT leakage, resulting in suppressing channel boosting. In order to overcome “Channel Coupling” appeared at 1X-nm node as a scaling barrier, the air gap in shallow trench isolation is suggested and the effect of the air gap is verified by simulation.

A new ruler on the storage market: 3D-NAND flash for high-density memory and its technology evolutions and challenges on the future

Scaling limitations in planar-NAND cell are discussed, including the depletion of floating gate and anomalous programming behavior. It is inevitable to have a paradigm shift to 3D-NAND due to numerous scaling limitations of planar NAND. However, the process complexity also increases in 3D-NAND as the mold height goes up in an exponential trend. Thus, scaling down of mold pitch is required, which degrades the cell characteristics. COP (Cell over Peripheral) 3D-NAND architecture has been developed as an area-scaling technology. CSL (Common-Source Line) junction leakage and p+ junction leakage at peripheral transistors have been improved by increasing the grain size and the thickness of barrier metal, respectively.

Highly reliable Cu interconnect strategy for 10nm node logic technology and beyond

CVD-Ru represents a critically important class of materials for BEOL interconnects that provides Cu reflow capability. The results reported here include superior gap-fill performance, a solution for plausible integration issues, and robust EM / TDDB properties of CVD-Ru / Cu reflow scheme, by iterative optimization of process parameters, understanding of associated Cu void generation mechanism, and reliability failure analysis, thereby demonstrating SRAM operation at 10 nm node logic device and suggesting its use for future BEOL interconnect scheme.