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Featured researches published by Jongmin Baek.


international interconnect technology conference | 2007

A Highly Reliable Cu Interconnect Technology for Memory Device

H.B. Lee; Jong Won Hong; G.J. Seong; Jung-hoo Lee; Heung-soo Park; Jongmin Baek; Kyung In Choi; B.L. Park; Jang-Yong Bae; Gil Heyun Choi; Sun-Rae Kim; U-In Chung; Joo Tae Moon; J.H. Oh; J.H. Son; J.H. Jung; Sang-rok Hah; Sang Yup Lee

This paper describes the development of Cu interconnect technology for memory devices. A highly reliable sub 50 nm Cu interconnect lines were successfully fabricated by using optimized iPVD barrier/seed and electroplating process. The resistivity of Cu lines was reviewed with that of Al for extendibility of Cu. The Cu TDDB lifetime in user conditions was investigated to confirm the reliability of Cu process integration. It can be predicted that Cu metallization can satisfy the requirements of sub 50 nm trench pattern, which are lower resistance than Al and good reliabilities.


international electron devices meeting | 2014

Highly reliable Cu interconnect strategy for 10nm node logic technology and beyond

R.-H. Kim; Byung-hee Kim; T. Matsuda; Jin-Gyun Kim; Jongmin Baek; Jong Jin Lee; J.O. Cha; J.H. Hwang; S.Y. Yoo; K.-M. Chung; Ki-Kwan Park; J.K. Choi; Eun-Cheol Lee; Sang-don Nam; Y. W. Cho; Hyoji Choi; Ju-Hyung Kim; Soon-Moon Jung; Do-Sun Lee; Insoo Kim; D. Park; Hyae-ryoung Lee; S. H. Ahn; S.H. Park; M.C. Kim; B. U. Yoon; S.S. Paak; N.I. Lee; J.-H. Ku; J-S Yoon

CVD-Ru represents a critically important class of materials for BEOL interconnects that provides Cu reflow capability. The results reported here include superior gap-fill performance, a solution for plausible integration issues, and robust EM / TDDB properties of CVD-Ru / Cu reflow scheme, by iterative optimization of process parameters, understanding of associated Cu void generation mechanism, and reliability failure analysis, thereby demonstrating SRAM operation at 10 nm node logic device and suggesting its use for future BEOL interconnect scheme.


international interconnect technology conference | 2013

Reliable integration of robust porous ultra low-k (ULK) for the advanced BEOL interconnect

Kyu-hee Han; Seungwook Choi; Tae Jin Yim; Seung-hyuk Choi; Jongmin Baek; Sang-hoon Ahn; Nae-In Lee; Si-Young Choi; Ho-Kyu Kang; Eunseung Jung

In order to address the increasing RC and reliability challenges at the advanced technology nodes, a new robust ULK was developed that incorporates the bridging carbon atoms (Si-[CH2]x-Si) in p-SiOCH matrix. Its elastic modulus and plasma damage resistance were improved more than 40% at the same dielectric constant than the commercially available ULK. These improvements are attributed to 80% higher atoms that exist in both Si-[CH2]x-Si and Si-CH3 structures with its pore size 23% smaller. Furthermore, its superb properties resulted in 3~4% capacitance reduction, and improvement of TDDB and EM TTF (time to failure) by 2 order and 2~3 times, respectively, on an advanced BEOL vehicle.


international electron devices meeting | 2013

Superior Cu fill with highly reliable Cu/ULK integration for 10nm node and beyond

T. Matsuda; Jong Jin Lee; K. H. Han; Ki-Kwan Park; J.O. Cha; Jongmin Baek; T.-J. Yim; Dong-Chan Kim; Do-Sun Lee; Jin-Gyun Kim; Seungwook Choi; Eun-Cheol Lee; Sang-don Nam; Hyae-ryoung Lee; Y. W. Cho; Insoo Kim; B. H. Kwon; S. H. Ahn; J. H. Yun; Byung-hee Kim; B. U. Yoon; J.S. Hong; N.I. Lee; S. Choi; Hyon-Goo Kang; E. S. Chung

It is possible to overcome Cu void issues beyond 10nm node device by adapting CVD-Ru liner instead of conventional PVD Ta liner. However, CVD Ru liner integration degrades TDDB performance without optimizing its scheme. In this paper, superior gap-fill performance without TDDB performance degradation will be described in our optimized integration scheme along with a proposal for the mechanism of TDDB degradation in the Ru integration scheme. CVD-Ru liner is the prime candidate for Cu metallization at 10nm node and beyond.


international interconnect technology conference | 2015

High performance Cu/low-k interconnect strategy beyond 10nm logic technology

R.-H. Kim; Byung-hee Kim; Jin-Gyun Kim; Jong Jin Lee; Jongmin Baek; J.H. Hwang; J.W. Hwang; J. Chang; S.Y. Yoo; T.-J. Yim; K.-M. Chung; Ki-Kwan Park; T. Oszinda; Insoo Kim; Eun-Cheol Lee; Sang-don Nam; Soon-Moon Jung; Y. W. Cho; Hyunjun Choi; Ju-Hyung Kim; Sang-hoon Ahn; Sun-hoo Park; B. U. Yoon; J.-H. Ku; S.S. Paak; N.I. Lee; S. Choi; Hyon-Goo Kang; Eunseung Jung

CVD-Ru based reflow Cu scheme demonstrates robust gap fill performance at 10nm and 7nm node equivalent patterns. Potential EM and TDDB reliability concerns associated with Ru CMP are identified and successfully addressed by the application of new processes and materials. This suggests our proposed scheme can be one of promising candidates for 10nm node logic device and beyond.


Archive | 2014

Semiconductor devices including a capping layer and methods of forming semiconductor devices including a capping layer

Sang-Ho Rha; Jongmin Baek; Wookyung You; Sang-hoon Ahn; Nae-In Lee


Archive | 2016

Semiconductor devices including a capping layer

Sang-Ho Rha; Jongmin Baek; Wookyung You; Sang-hoon Ahn; Nae-In Lee


Archive | 2016

Methods of Forming Wiring Structures and Methods of Fabricating Semiconductor Devices

Wookyung You; Sang-Ho Rha; Jongmin Baek; Sang-hoon Ahn; Nae-In Lee


Archive | 2014

Wiring structures and methods of forming the same

Jongmin Baek; Sang-Ho Rha; Wookyung You; Sang-hoon Ahn; Nae-In Lee; Ki-chul Kim; Jeon-II Lee


Archive | 2016

SEMICONDUCTOR DEVICES HAVING STAGGERED AIR GAPS

Sang-Ho Rha; Jongmin Baek; Wookyung You; Sang-hoon Ahn; Nae-In Lee

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