F. De Bernardinis

Benefits and challenges for platform-based design

Platforms have become an important concept in the design of electronic systems. We present here the motivations behind the interest shown and the challenges that we have to face to make the Platform-based Design method a standard. As a generic term, platforms have meant different things to different people. The main challenges are to distill the essence of the method, to formalize it and to provide a framework to support its use in areas that go beyond the original domain of application.

A dither-less all digital PLL for cellular transmitters

Frequency synthesizer for cellular transmitters demands low phase-noise both in-band and out-of-band. The first is necessary to implement wideband modulations (e.g. WCDMA), while the second to satisfy the challenging emission mask of GSM. Moreover a low level of fractional spurs must be ensured. The paper describes the first dither-less ADPLL capable to satisfy all these requirements. These results are achieved exploiting a highly linear 2-dimension Vernier TDC and a very fine frequency resolution DCO. Both building blocks heavily rely on digital calibration techniques to precisely and efficiently implement two-point modulation and spur cancellation in the presence of many implementation impairments.

A complete DVB-T/ATSC tuner analog base-band implemented with a single filtering ADC

A filtering ADC used to implement the complete base-band in a receiver chain is presented. Passive filtering and in-band noise shaping lead to a frequency dependent dynamic range that better fits with the system requirements of a wireless receiver. The 90nm CMOS prototype is embedded in a fully integrated tuner compliant with DVB-T and ATSC standards. For a 6MHz channel bandwidth, the filtering ADC exhibits a frequency dependent dynamic range varying from 75.6dB to 90dB while drawing 30mA from a 1.8V supply.

Wireless protocols design: challenges and opportunities

Modern wireless communication systems require the deployment of increasingly complex protocols that satisfy tight requirements at low implementation cost, especially in terms of size and power consumption. Most protocol design methodologies currently in use are inadequate, either because they do not rely upon formal techniques and therefore do not guarantee correctness, or because they do not provide sufficient support for performance analysis and design exploration and therefore often lead to sub-optimal implementations. Therefore, we use a refinement-based formal methodology that relies upon the orthogonalization of function and architecture design and emphasizes the use of formal models to ensure correctness and reduce design time. In this paper we present a case study, the Intercom, consisting of a network of mobile terminals supporting voice communication among end users. We use this case study to validate the methodology and identify directions of further research.

Designing wireless protocols: methodology and applications

Communication protocols are essential components of wireless systems. Present methods for protocol design are heuristic in nature and are not suited for next generation wireless systems where time-to-market concerns require correct-the-first-time implementations. In this paper we present a new design methodology for wireless protocols based on the principle of orthogonalization of concerns. In particular, the methodology separates function and architecture design and emphasizes the use of formal models to ensure correctness and reduce design time. Protocols are described using co-design finite state machines (CFSMs), a model of computation that has been introduced to allow the efficient capture of both the control and the data processing parts of the specification. Furthermore, algorithms for automatic hardware and software synthesis from CFSMs are available. This allows a fast exploration of different HW/SW partitions and the analysis of tradeoffs involved. Intercom, a mobile wireless system supporting full-duplex voice communication among different users, is presented and the design of its protocols is described. The design methodology presented here will be used for the design of PicoRadio, a low-power and highly adaptive network of sensors.

A methodology for system-level analog design space exploration

This paper describes a novel approach to system level analog design. A new abstraction level - the platform - is introduced to separate circuit design from design space exploration. An analog platform encapsulates analog components concurrently modeling their behavior and their achievable performances. Performance models are obtained through statistical sampling of circuit configurations. The design configurations space is specified with analog constraint graphs so that the sampling space is significantly reduced. System level exploration can be achieved through optimization on behavioral models constrained by performance models. Finally, an example is provided showing the effectiveness of the approach on a WCDMA amplifier.

Efficient analog platform characterization through analog constraint graphs

We propose a scheme for improving the efficiency of the characterization process for system-level models of analog circuits within the analog platform based design paradigm. We leverage designer knowledge to map basic functional requirements of the circuit into circuit parameters relations so that the sampling space can be significantly reduced. A set of equalities and inequalities in the circuit parameters is used to represent the constraints. A feasible parameter space lies at the intersection of the sets of design parameters that satisfy equalities and inequalities, defining a manifold in the parameter space. We introduce a bipartite graph representation denoted analog constraint graphs (ACG) to represent these constraints. ACGs are instrumental for obtaining a random configuration generator that samples configurations in the manifold. The sampler is automatically translated into executable code to fit the characterization framework starting from a mathematical description of constraints. Results show that the automatically generated samplers are comparable in terms of code efficiency with hand-written ones. Furthermore, a heuristics to generate uniformly distributed configuration enabled by the tools is presented and applied to a complex ADC design, yielding a reduction in power consumption by more than 28%.

Enriching an analog platform for analog-to-digital converter design

Platform-based analog design is used to design an analog-to-digital converter reducing power consumption by 26%. This result was achieved by enriching the library of analog components used as the basis of the design with a telescopic operational transconductance amplifier (OTA). We present the way in which the models for this new component necessary to use platform based design can be added quickly and efficiently with the use of analog constraint graphs.

A low-power mixed-signal baseband system design for wireless sensor networks

We present the design methodology and a silicon implementation of a baseband system for use in wireless sensor network applications. Starting from the RF interface, our design process began with a system level phase inspired by the platform-based design (PBD) methodology extended to the analog domain. The functional design was based on an early-late gate synchronization scheme. The PBD approach was used to explore two alternative solutions: a predominantly digital one and a predominantly analog one. To validate the functional aspect of the design, a prototype implementation based on an FPGA and a field programmable analog array (FPAA) was derived using the PBD approach. Finally, we mapped the system level description to silicon aiming at an ultra low power implementation exploiting weak inversion in a 0.13/spl mu/CMOS process leading to an overall power consumption of 200/spl mu/W with a 1V supply.

A single-chip 1,200 sinusoid real-time generator for additive synthesis of musical signals

This paper presents a new hardware implementation of additive synthesis for high quality musical sound generation. The single-chip configuration is capable of performing 1,200 sinusoid real-time synthesis; the system is expandable to 13,200 partials by series connecting 11 chips. Each sinusoid is generated by a marginally stable second order IIR filter, and its frequency, amplitude and phase can be independently specified. The system is clocked at 60 MHz when working with a 44.1 kHz sampling rate. Two completely independent channels are available as output, and each sample relies on a 20 bit representation to achieve an SNR of at least 110 dB, thanks to the internal 24 bit word length. The IC is designed in a 0.5 /spl mu/m CMOS technology and has a core area of approximately 19 mm/sup 2/.