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A CMOS Ultra-Wideband Receiver for Low Data-Rate Communication

A low-power impulse-radio ultra-wideband receiver is demonstrated for low data-rate applications. A topology selection study demonstrates that the quadrature analog correlation is a good receiver architecture choice when energy consumption must be minimized. The receiver operates in the 3.1-5 GHz band of the UWB FCC spectrum mask on channels of 500 MHz bandwidth. The pulse correlation operation is done in the analog domain in order to reduce the ADC sampling speed down to the pulse repetition rate, thereby reducing the power consumption. The receiver comprises a low-noise amplifier with full on-chip matching network, an RF local oscillator generation, two quadrature mixers, two analog baseband chains followed by two ADCs, and a clock generation network. The receiver is implemented in 0.18 mum CMOS technology and achieves 16 mA power consumption at 20 Mpulses/s pulse repetition rate.

A 16mA UWB 3-to-5GHz 20Mpulses/s Quadrature Analog Correlation Receiver in 0.18/spl mu/m CMOS

A 3-to-5GHz quadrature analog correlation RX for UWB impulse radio draws 16mA at 20Mpulses/s, making it suitable for low-power low-data-rate applications. The RX is fully integrated in a CMOS 0.18mum process and comprises an LNA, quadrature LO generation and mixers, baseband filtering, an integrator, timing circuitry, and an ADC

Mixed signal design space exploration through analog platforms

We propose a hierarchical mixed signal design methodology based on the principles of platform-based design (PBD). The methodology is a meet-in-the-middle approach where design components are modeled bottom-up at various abstraction levels and performance constraints are mapped top-down to select among the available components the ones that best meet the constraints. The design methodology can seamlessly operate on both analog and digital designs, thus dealing with mixed signal designs in a consistent way. We demonstrate the effectiveness of the approach optimizing an 80 MS/s 14 bit pipelined analog-to-digital converter (ADC) including digital calibration, yielding 64% power reduction compared to the original hand optimized design.

Efficient Calibration through Statistical Behavioral Modeling of a High-Speed Low-Power ADC

We address the problem of calibrating a flash analog-to-digital converter (ADC) for ultra-wide band energy-constrained receivers. To achieve a superior power efficiency the ADC exploits an unusual comparator architecture that is capable of avoiding the reference ladder, but need threshold calibration for offset compensation. In this work, we present a foreground calibration technique, which aims at reducing the required energy by minimizing the number of clock cycles required for calibration. Optimization is performed relying on a fast and accurate ADC statistical behavioral model, which is also useful to characterize different calibration schemes and provide feedback to the system designer, avoiding expensive electrical simulations. The proposed technique is successfully applied to a 4-bit 90nm CMOS ADC prototype, obtaining INL< 0.15LSB, DNL<0.2LSB and 3.7-ENOB at 1.25GS/s at the expense of only 15.17nJ ADC energy

A 10.6mW/0.8pJ power-scalable 1GS/s 4b ADC in 0.18/spl mu/m CMOS with 5.8GHz ERBW

We present a 4-bit power scalable flash analog-to-digital converter in digital 0.18-μm CMOS, targeting low power ultra-wide band receivers. To minimize static power consumption, we exploit dynamic comparators with built-in digitally tunable thresholds. The converter has been realized and tested outperforming recent comparable designs even in more advanced technologies. The main performance figures include 5.8GHz effective resolution bandwidth and 0.8pJ/conversion-step at 1-GS/s and Nyquist conditions.

Robust system level design with analog platforms

An approach to robust system level mixed signal design is presented based on analog platforms. The bottom-up characterization phase of platform components provides accurate performance models that export architectural constraints to the system level. From the one side, performance models can be affected by residual errors and usually do not consider process variations and modeling uncertainties. Conversely, behavioral models cannot match accurate circuit level simulations, so that during the mapping (exploration) process circuit configurations difficult to be realized may be obtained. We propose a methodology that extends techniques from optimization and design centering to system level analog design exploiting general, implicit architectural constraints to control the robustness of the solution. The approach allows quantitative extension of robust techniques to hierarchical designs. Its effectiveness is illustrated with the design of a pipeline A/D converter and a UMTS receiver front-end

Enriching an analog platform for analog-to-digital converter design

Platform-based analog design is used to design an analog-to-digital converter reducing power consumption by 26%. This result was achieved by enriching the library of analog components used as the basis of the design with a telescopic operational transconductance amplifier (OTA). We present the way in which the models for this new component necessary to use platform based design can be added quickly and efficiently with the use of analog constraint graphs.

A Synthesis Tool for Power-Efficient Base-Band Filter Design

A baseband filter synthesizer that takes a behavioural description of the design and produces an efficient transistor level implementation is presented. The tool optimizes the filter at the cascade level, providing the best trade-off between power consumption and dynamic range, and at the cell level, selecting minimum power solutions, through accurate analytical models and an efficient bi-quad topology. Differently from past cascade design techniques based on dynamic range optimization through linear programming, we focus on power minimization while guaranteeing minimum performance levels, given the increasing importance of power savings in hand-held devices. A synthesized filter has been realized in silicon demonstrating the effectiveness of our approach

Efficient Polynomial Inversion for the Linearization of Pipeline ADCs

We present an efficient solution to the digital enhancement of the characteristic of pipeline analog-to-digital converters (ADCs) given estimates for non-linearity behaviors. A third order polynomial model is assumed for non-linearity and several inversion mechanisms are analyzed in terms of complexity and power consumption. Two efficient implementations based on a predictor-corrector scheme and on Newton-Raphson iterations are presented. Missing codes appearing after linearization are emphasized and the benefits of increasing resolution are shown. Limitations of linearization techniques are finally reported in terms of achievable ENOB and SFDR