F.H. Ruddell

Development of monolithic active pixel sensor in SOI Technology fabricated on the wafer with thick device layer

Monolithic active pixel detectors fabricated in SOI (Silicon On Insulator) technology are novel sensors of ionizing radiation, which exploit SOI substrates for the integration of readout electronics and a pixel detector. The fully depleted sensing diode has been manufactured under buried oxide (BOX) while read-out circuitry occupies upper silicon layer (‘device layer’). The development of the SOI detectors of ionizing radiation was started as a part of the SUCIMA project. During the project, it was proved that a monolithic SOI detector is a viable option for high-energy physics and medicine. The early prototypes suffered from significant leakage currents and soft breakdowns. These effects limited yield of production. Moreover, the p-wells (formed within the device layer and extended to the interface with the BOX), caused some local potential wells below the BOX at the top of depleted sensor area reducing the effective charge collection efficiency. The use a thicker device layer and optimized technology appeared to be a remedy.

Germanium on sapphire

This paper explores the potential of germanium on sapphire (GeOS) wafers as a universal substrate for System on a Chip (SOC), mm wave integrated circuits (MMICs) and optical imagers. Ge has a lattice constant close to that of GaAs enabling epitaxial growth. Ge, GaAs and sapphire have relatively close temperature coefficients of expansion (TCE), enabling them to be combined without stress problems. Sapphire is transparent over the range 0.17 to 5.5 μm and has a very low loss tangent (α) for frequencies up to 72 GHz. Ge bonding to sapphire substrates has been investigated with regard to micro-voids and electrical quality of the Ge back interface. The advantages of a sapphire substrate for integrated inductors, coplanar waveguides and crosstalk suppression are also highlighted. MOS transistors have been fabricated on GeOS substrates, produced by the Smart-cut process, to illustrate the compatibility of the substrate with device processing.

LRP equipment characterisation at low temperatures and application to polysilicon bipolar emitter processing

A plasma-stimulated LPCVD rapid thermal processor has been developed. This processor is capable of operation in the limited reaction processing (LRP) regime and offers sequential in situ processes such as silicon deposition, plasma oxidation and interface pre-cleaning. Incident power with wavelength greater than 1.1 mu m is absorbed by free carriers and therefore sample doping density has a strong effect on the temperature-time profile obtained. It has been shown experimentally that heavily doped n-type samples reach higher temperature than lightly doped samples and exhibit faster ramp up times. The doping dependence is not so strongly observed for p-type samples. However, in general p-type samples do not attain as high a temperature as n-type samples. This is believed to be due to an additional absorption band for n-type silicon centred around wavelengths of 2.3 mu m. Direct monitoring of the process wafer is considered essential for accurate temperature-time profiles. The system has been used to fabricate n-p-n polycrystalline silicon emitter bipolar transistors. Transistors which received an in situ CF4 plasma pre-clean prior to polysilicon deposition exhibited gains similar to reference long emitter devices. The results were characterised by excellent uniformity across the samples indicating a clean, well controlled interface between the polysilicon and the silicon. This is highly important if LRP systems are to be applied to low-temperature epitaxy and heterojunction production on silicon. Transistors which received an in situ plasma clean, plasma oxidation followed by polysilicon deposition schedule exhibited higher gains. This supports the theory that the thin tunnellable oxide between the polycrystalline and monocrystalline silicon is responsible for the increased gain in the polysilicon emitter devices.

Novel materials for the semiconductor industry, deposited using a rapid thermal chemical vapour deposition system

Abstract This paper describes a custom-built rapid thermal chemical vapour deposition system developed to allow the growth of silicon and silicon carbide at low pressure and with minimal thermal budget. The reactor uses tungsten-halogen lamps to heat the single process wafer to a maximum temperature of 1080°C with a maximum rate of 250°C/s. A microwave magnetron provides gas plasma chemistry capability. Silicon layers with low oxygen contamination are produced at around 720°C and 0.07 mbar using silane. Silicon carbide is deposited at around 970°C and 10 mbar using silane/propane chemistry. Both processes incorporate a CF4 plasma clean of the wafer surface prior to deposition. Bipolar transistors produced with a silicon carbide emitter gave higher gains than standard reference devices.

Circular geometry mos transistor analysis of SOI substrates for high energy physics particle detectors

SOI substrates are important for the fabrication of monolithic active pixel high energy physics particle detectors. In this work, self-aligned circular geometry MOS transistor test structures were fabricated on ion split, bonded SOI substrates to evaluate the interface between the high resistivity handle silicon and the SOI buried oxide. Pre- and post- proton irradiation transistor measurements are presented, showing an increased SOI buried oxide trapped charge of only 3.45times1011 cm-2 for a dose of 2.7 Mrad.

Silicon carbide layers produced by rapid thermal chemical vapor deposition

A rapid thermal CYD reactor has been employed for the deposition of silicon carbide layers on silicon. Stoichiometric SiC layers were deposited using silane/propane gas chemistry over the temperature range 720-970C. The process wafer was ramped rapidly to the deposition temperature after gas flows were established. The deposition was thus temperature activated so that minimum thermal budgets were obtained. The influence of both process pressure and the silane/propane gas flow ratio on carbon and oxygen content in the films was determined. The critical conditions for the deposition of stoichiometric silicon carbide with minimum oxygen content and without an interfacial oxide layer have been determined. In-situ doping with phosphine has been employed to deposit SiC layers with a phosphorus concentration of 5x1020cm3 and a resistivity of O. 6ohm. cm. Heterojunction silicon bipolar transistors were fabricated with deposited SiC layers for the emitters. While some enhancement was obtained for transistors with oxygen contaminated emitters those with purer emitters had common emitter gains of less than unity. This has been attributed to a reduction in base lifetime due to a carbonisation tail.