F. Montecchi

Low-voltage analog filters

This paper reviews the design of analog filters at low supply voltage. In particular, the main focus is on switched capacitor and g/sub m/-C type filters because, at the present time, they have the greatest commercial importance. SC implementations are discussed in the context of low frequency high precision applications while g/sub m/-C implementations are discussed in the context of high frequency medium/low precision applications. Both fundamental and practical limitations to the achievable dynamic range at low supply voltage are explained. The paper reviews well established circuit and architectural techniques as well as some promising new ones that might result in performance improvements in the future.

A 10.7-MHz BiCMOS high-Q double-sampled SC bandpass filter

A fundamental block in telecommunication systems is the high-selectivity bandpass filter centered at the intermediate frequency (IF). In this paper, a BiCMOS high-Q (Q=29) 10.7-MHz switched-capacitor (SC) bandpass filter to be used in the FM receiver channel has been developed. The filter uses low-gain large-bandwidth opamps. The opamp finite gain effects have been compensated using an SC integrator suited for high-Q filters. The particular SC finite-gain compensation scheme allows the implementation of double sampling to relax opamp bandwidth requirements. To reduce total output noise, noisy T-cell networks (often used in other cases) have been avoided. The resulting large capacitors (the largest capacitor is 8.5 pF) are driven by a Class AB output buffer. In a 1.2-/spl mu/m BiCMOS technology, the filter prototype has an area of about 1.6 mm/sup 2/ and a power consumption of 17 mW. The in-band noise density is 380 nV//spl radic/Hz, and the dynamic range is about 68 dB for a 3% IM.

Finite gain compensated double-sampled switched-capacitor integrators for high-Q bandpass filters

A technique for the compensation of the operational amplifier (op-amp) finite gain error in the switched-capacitor (SC) integrator is proposed. Two possible SC integrators implementing the proposed technique are given. Both implementations allow the use of the double-sampling technique to increase by a factor of two the maximum speed of operation. The compensation operation consists in memorizing a sequence of output values of the SC integrator, and using them in the proper clock period to compensate the error due to the nonideal virtual ground. The compensation is mostly effective in a narrow frequency range centered around one specific frequency. The circuits implementing this technique are therefore particularly useful for high-Q high-frequency bandpass filters. The case of a biquadratic bandpass filter is reported as an example. >

A very linear BiCMOS transconductor for high-frequency filtering applications

A differential transconductance stage implemented in BiCMOS technology is described. The key features of the new stage are: (1) a total harmonic distortion (THD) less than 0.15% up to a 3 V/sub pp/ differential input signal, assuming 2% mismatch of the input devices, with a 5-V supply; (2) a second pole frequency typically higher than 2 GHz; and (3) a gain of more than 50 dB. All of these features are obtained from simulations performed using SPICE and correspond to a BiCMOS process featuring 2- mu m minimum channel length and 7-GHz bipolar f/sub T/. The structure of the transconductance is described and its operation explained. The nonidealities of the stage, like distortion, finite gain, parasitic poles, noise, and offset, are discussed. The complete implementation is presented. The simulated performance of a bandpass filter based on the new transconductor is reported. The results demonstrate that using the new circuit a filter centered around 5 MHz with a Q of 22 should result in a Q precision better than 12% without any Q tuning.<<ETX>>

Noise performances of OTA-C filters

Noise performances of OTA-C (operational transconductance amplifiers and capacitors) filters are presented in order to derive their dynamic range limitations. In particular, the noise performances of elementary building blocks are considered, and then the noise of several OTA-C biquadratic structures is evaluated. Both white and 1/f noise contributions are taken into account. Analytical expressions and simulated results are given together with some practical design considerations. The results put in evidence how the choice of any topology affects the noise limitations of the filter. Topologies that allow more degrees of freedom correspond to noisier structures.<<ETX>>

Accurate MOS threshold voltage detector for bias circuitry

A circuit for the detection of the threshold voltage V/sub TH/ of MOS devices is presented. The basic scheme proposed here is implemented in BiCMOS technology but can also be applied in any standard CMOS process. The deviation of the detected V/sub TH/ from the actual (or extrapolated) one is analytically estimated, taking into account the effects due to channel length modulation and mobility modulation. The results obtained show that the error at ambient temperature is lower than 0.6% for all values of V/sub DD/ larger than 3.25 V, and for temperatures in the range -25 degrees C to 125 degrees C the error is never higher than 4%.<<ETX>>

A 15 MHz 20 mW BiCMOS switched-capacitor biquad operating with 150 Ms/s sampling frequency

In order to increase the sampling frequency of SC filters the Precise Opamp Gain (POG) design approach is presented. It is based on the use of large bandwidth opamps with low but precise DC gain. The finite gain value is taken into account in the design phase. This produces capacitor values slightly different from those obtained with the standard design. A BiCMOS opamp with a nominal gain of 96 and unity-gain frequency of 650 MHz is used in a biquadratic lowpass filter with Q=2.8 designed with the POG approach. In a 1.2 /spl mu/m BiCMOS technology, the prototype lowpass biquad operates with sampling frequency up to 150 Ms/s with 0.2 dB accuracy in the transfer function. For a sampling frequency of 150 Ms/s, the cut off frequency is 15 MHz. The dynamic range (for 1% THD) is 67 dB, and THD is less than -60 dB for a 1.5 Vpp 5 MHz input signal. The chip area is 1 mm/sup 2/, and the power consumption is 20 mW.

A tunable switched-capacitor programmable N-path tone receiver and generator

An integrated full-duplex tone receiver and generator used for signaling in mobile radio systems and realized with a switched-capacitor pseudo N-path technique is described. A receiver filter with a quality factor programmable in the range 10-230 with an in-band loss less than 0.2 dB and center frequencies from 1 Hz up to 10 kHz was achieved. The tone generator of the system was realized with a programmable gain switched-capacitor amplifier that generates an eight-sample pseudo-sine-wave signal. The chip was fabricated using a 3- mu m double-poly CMOS process. Its power consumption is 17 mW with a single 5-V supply, and its size is 18 mm/sup 2/. >

Finite gain compensation techniques for high-Q bandpass SC filters

A technique for the compensation of the finite gain in a switched-capacitor (SC) integrator is presented. The technique is effective in a narrow frequency range centered around a specific frequency. The finite-gain compensation technique is derived from the basic idea of memorizing the values of the output signal of SC integrator and using them to predict the operation of the stage in the successive time slots. The operation is based on the memorization of the effects caused by the finite gain at that frequency, and on the use of this information for compensating purposes. The circuits are particularly suited for high-Q high-frequency bandpass filters. An example of a biquad is reported.<<ETX>>

A 1 V 1.2 /spl mu/W 4th order bandpass switched-opamp SC filter for a cardiac pacer sensing stage

A 4th-order bandpass switched-capacitor (SC) filter to be used as a part of an implantable device has been designed. The power consumption reduction is a key feature of such a system. This has been achieved by using a 1 V supply (SC operation are guaranteed by using the switched-opamp technique). In addition the active devices operate in the subthreshold region. The filter uses a fully differential topology to reduce the clock feedthrough noise and increase the dynamic range. The filter has been designed in a 0.35 /spl mu/m CMOS technology. It operates at 1 kHz sampling frequency and it consumes about 1.2 /spl mu/W.