G. Palmisano

An accurate CMOS sample-and-hold circuit

An accurate sample-and-hold (S/H) circuit implemented with a 2- mu m double-poly CMOS process is described. Competitive performance in terms of output swing, linearity, and clock feedthrough compensation was obtained using a new circuit topology. The sample and hold operates up to 1 MHz of sampling frequency with less than -60 dB of total harmonic distortion. The accuracy of the held step is better than 0.2 mV. The circuit dissipates 4 mW with a 5-V power supply. >

A tunable switched-capacitor programmable N-path tone receiver and generator

An integrated full-duplex tone receiver and generator used for signaling in mobile radio systems and realized with a switched-capacitor pseudo N-path technique is described. A receiver filter with a quality factor programmable in the range 10-230 with an in-band loss less than 0.2 dB and center frequencies from 1 Hz up to 10 kHz was achieved. The tone generator of the system was realized with a programmable gain switched-capacitor amplifier that generates an eight-sample pseudo-sine-wave signal. The chip was fabricated using a 3- mu m double-poly CMOS process. Its power consumption is 17 mW with a single 5-V supply, and its size is 18 mm/sup 2/. >

Harmonic distortion in SC sigma-delta modulators

The maximum achievable resolution in noise-shaping modulators is a function of three principal parameters: oversampling ratio, M; noise-shaping order, L; and quantizer resolution, N. For practical implementations, thermal noise in MOS switches and amplifiers, bandwidth and slew-rate in integrator circuits in switched-capacitor (SC) implementations, and jitter noise in continuous-time (CT) and mixed CT-SC realizations have to be considered. This paper deals with harmonic distortion, which is a third design constraint in high-resolution SC noise-shaping modulators. Here we analyze harmonic distortion due to the nonideal DC-gain characteristic of operational amplifiers and derive a relationship for a standard SC integrator. Simulation results from a behavioral simulator we have developed validate the analysis. >

Integrated digital modulator and analog front-end for GSM digital cellular mobile radio system

An integrated circuit for the GSM (Group Special Mobile) digital mobile radio system which performs the GMSK (Gaussian minimum shift keying) modulation and the analog front-end functions is presented. The circuit was fabricated using a 2- mu m, double-poly, double-metal CMOS process. Its peak dissipation is 180 mW with a single 5-V supply. The die size is 6.7 mm*5.3 mm. The integrated circuit can be employed both in base and mobile stations, between the baseband digital processing and the 900-MHz radio frequency sections. The circuit performance fully meets GSM specifications.<<ETX>>

An integrated circuit for GSM mobile communications

An integrated circuit for the Pan European GSM mobile communications system is described which performs GMSK digital modulation and front-end functions for both base and mobile stations. The circuit includes, as main functional blocks, a 10-bit D/A converter, a 13-MHz switched-capacitor interpolating filter, and a power buffer. A fully differential approach was used. The circuit has been fabricated using a 2-μm CMOS process. The chip size is 6.7×5.3 mm2. The overall circuit performance fully meets GSM specifications.

A High Frequency CMOS Power Buffer with Extended Linearity

A CMOS power buffer suitable for high frequency applications is discussed. The use of a high-speed push-pull output stage and a highly-linear common mode feedback allow good linearity to be maintained even with very high input frequencies. Indeed, Total Harmonic Distortions (THD) as good as ¿66 dB and ¿58 dB are achieved at 0.5 MHz and 1 MHz, respectively, with a load resistance of 75 ¿. Moreover, the circuit provides a dc gain of 62 dB and a gain-bandwidth product of 60 MHz. The integrated prototype, realized using a 1.2 ¿m CMOS process, occupies a silicon area of 280 mils2.

Integrated frame generator and modulator for GSM digital cellular mobile radio system

An integrated circuit for the Pan-European Groupe Speciale Mobile (GSM) digital radio systems is described which performs the modulation and front-end functions for both base and mobile stations. The circuit, fabricated using a 2- mu m CMOS technology, fully meets the GSM requirements. The system uses Gaussian minimum-shift keying (GMSK) modulation, with a 0.3 modulation index, which is characterized by a narrowband spectrum. The circuit dissipates 180 mW with a single 5-V supply. The die size is 6.7 mm*5.3 mm.<<ETX>>

Custom integrated circuits for audio processing and signalling in vehicular units

The circuitry for the audio signal and subaudio signalling processing on the new vehicular unit for Italian Mobile Radio System is described. The overall system was realized with two different kinds of CMOS custom circuits and a few other discrete components. The two chips were designed with the switched capacitor (SC) technique and integrated in a 3u double poly CMOS technology. The system is fed by a 5V single power supply and dissipates about 140 mW.

An integrated solution for audio processing and signalling in mobile radio systems

An implementation of the circuitry for the audio signal and subaudio signalling processing on the Italian Mobile Radio System is described. The overall system was realized with two different CMOS custom circuits and a few other discrete components. The two chips were designed with the switched capacitor (SC) technique and integrated in a 3µ double poly CMOS technology. The system dissipates about 140 mW with a 5V single power supply.