Fahmi Ghozzi

Optimization and Implementation on Fpga of the DCT/IDCT Algorithm

In this paper, we present a comparison between two methods, the modified Loeffler algorithm (11 MUL and 29 ADD) and distributed arithmetic, to implement the DCT/IDCT algorithm for MPEG or H.26x video compression using VHDL description language. The implementation has been achieved on Altera Stratix EP1S10 FPGA which provides a dedicated DSP blocks required for common signal processing functions. A new solution based on this DSP blocks used to implement multipliers for the modified Loeffler algorithm in order to optimize speed and area

Hardware platform design for real-time video applications

In this paper, we present the installation of a hardware platform for video acquisition and restitution in real-time using a mixed software/hardware environment. The hardware platform is based on the Altera STRATIX development board. Besides, it is completed with a camera interface for acquisition and a VGA interface for restitution. The core of the system incorporates an IP module (intellectual property) of Altera Nios processor in the Quartus II development tool of Altera. During this study, we have used video sequences, which are acquired, processed and visualized while respecting temporal constraints.

HW/SW Codesign of the H. 263 Video Coder

In this paper, we propose an optimized real-time H.263 video coder. The coder has been implemented in one FPGA device as HW/SW partitioned system. We made time analysis and optimization of the H.263 coder. On the basis of the achieved results, we decided for hardware implementation of the discrete cosine transform (DCT). Remaining parts were realized in software with NIOS II softcore processor. H.263 coder (NIOS II processor, DCT core) has been described by the VHDL language and implemented in Stratix EP1S10 FPGA. Finally, the coder has been tested on the Altera Stratix development board

An Efficient HW/SW Implementation of the H.263 Video Coder in FPGA

In this paper, we present an efficient HW/SW codesign architecture for H.263 video coder and its FPGA implementation. Each module of the coder is investigated to find which approach between HW and SW is better to achieve real-time processing speed as well as flexibility. The hardware portion include the discrete cosine transform (DCT) and inverse DCT (IDCT). Remaining parts were realized in software with NIOS II softcore processor. This paper also introduces efficient design methods for HW and SW modules. In hardware, an efficient architecture for the 2-D DCT and 2-D IDCT is suggested to reduce the chip size. Software optimization technique is also explored by using the fast block-matching algorithm for motion estimation (ME). The whole design are described in VHDL language and implemented in stratix EP2S60 FPGA. Finally, the coder has been tested on the altera NIOS II development board.