Sameh Ibrahim

Low-Power CMOS Equalizer Design for 20-Gb/s Systems

The power consumption of wireline circuits has become increasingly more critical as the pin count and data rate rise. This paper describes a power scaling methodology and a new half-rate speculative architecture for decision-feedback equalizers (DFEs) to relax the speed-power trade-offs. Designed in 90-nm CMOS technology, a 20-Gb/s prototype consisting of a linear equalizer and a one-tap DFE compensates for the loss of an 18-in FR4 trace while drawing 40 mW from a 1-V supply.

A 20Gb/s 40mW equalizer in 90nm CMOS technology

In order to reduce the pin count of chips and the complexity of the routing on printed-circuit boards and backplanes, it is desirable to replace a large number of parallel channels with a few serial links. Such a transformation can also potentially save significant power because it lowers the number of output drivers while maintaining the I/O voltage swings and termination impedances relatively constant. It is therefore plausible that data rates approaching 20 Gb/s will become common in the near future. At these speeds, the loss of FR4 boards poses a great challenge, requiring heavy equalization. From circuit design point of view, it is simpler to employ linear equalization (in the transmitter and the receiver), but from system design point of view, two serious issues make this approach unattractive: the amplification of crosstalk and the lack of ability to equalize for impedance discontinuities (sharp notches in the channel frequency response). In an optimum, yet practical system, one would place 4 to 5 dB of linear equalization in the transmitter and a similar amount in the receiver, and perform the remaining equalization by means of a decision-feedback equalizer (DFE), thus alleviating both issues.

A 15.5-mW 20-GSps 4-bit charge-steering flash ADC

This paper presents a 4-bit 20-GSps time-interleaved flash ADC for an ADC-based high-speed serial-link equalizer. The ADC is designed and simulated in a 65-nm CMOS technology. It dissipates 15.5 mW from a 1-V supply while operating at 20 GSps. Low power consumption is achieved by utilizing charge-steering concept, sharing single reference ladder across all the four interleaved branches, and merging the dynamic latch into the pre-amplifier of the comparator. Results show that for a sinusoidal input frequency of 9.84 GHz with an amplitude of 600 mVdiff, the SNDR of the digital output is 23.9 dB, SFDR is 33.6 dB, and the effective number of bits (ENOB) is 3.67 bits.

A low-power, 9-Bit, 1.2 ps resolution two-step time-to-digital converter in 65 nm CMOS

This paper presents the design of a low-power, 9-bit, two-step time-to-digital converter (TDC) in 65 nm CMOS. Instead of using an array of time amplifiers (TAs) to amplify the time residue, the proposed TDC reduces the power and area consumptions by using only one TA. The designed TDC achieves a resolution of 1.2 ps with a conversion range of 0.614 ns while consuming 0.602 mW at 10 MHz and 8.299 mW at 150 MHz. The achieved figure-of-merit (FoM) of the TDC is 0.108 pJ/conversion at a frequency of 150 MHz.

A novel current steering charge pump with low current mismatch and variation

A charge pump circuit to minimize current mismatch and current variation over a wide voltage compliance range is proposed. A feedback loop is used to cancel both deterministic and random mismatches between charging and discharging current to minimize PLL reference spurs and static phase offset. A current compensation circuit is used to minimize current variation to avoid bandwidth variation and loop instability. The circuit can operate at low supply voltage. The power overhead due to added circuitry is 3.36% making it suitable for low-power and low-voltage applications. The proposed current-steering charge pump circuit achieves mismatch lower than 0.44% over the output voltage range from 0.06 V to 0.85 V. Also the current variation is reduced to less than 1.19% when the output voltage varies from 0.06 V to 0.85 V in the 65 nm CMOS process with 1 V supply.

A 24-mW 65-nm CMOS TI-Flash ADC for multi-standard serial-link receivers

A 4-channel 4-bit flash analog-to-digital converter is presented with 10Gbps sampling speed and a figure-of-merit of 182 fJ/conversion-step. It uses a conventional clocking scheme, along with a modified sample-and-hold and comparator chain circuits that reduce the overall ADC power consumption, and enhances both the resolution and accuracy without the need for any digital calibration. The ADC is designed using 65-nm CMOS technology and tested for input signals up to 5 GHz with ENOB of 3.7 bits. The reported DNL and INL are 0.42 LSB. The ADC channels are programmable to provide optimum power consumption for multi-standard serial-link applications. The latency for each sub-ADC output is about one and half clock cycle.

Design requirements of 20-Gb/s serial links using multi-tone signaling

The use of multi-tone signaling can avoid the high loss of FR4 traces beyond 10 GHz while confining the task of equalization to 2.5-GHz-wide subchannels. This paper presents multi-tone transceiver design issues and derives performance requirements such as linearity, sensitivity, quadrature mismatches, and phase noise. Possible transmitter and receiver implementations are described and a critical interference effect resulting from local oscillator harmonics is identified.

Design and analysis of a low-power high-speed charge-steering based StrongARM comparator

This paper presents an ultra low-power high-speed dynamic comparator. The proposed dynamic comparator is designed and simulated in a 65-nm CMOS technology. It dissipates 7 μW, 21.1 μW from a 0.9-V supply while operating at 1 GHz, 3 GHz sampling clock respectively. Proposed circuit can work up to 14 GHz. Ultra low power consumption is achieved by utilizing charge-steering concept and proper sizing. Monte Carlo simulations show that the input referred offset contribution of the internal devices is negligible compared to the effect of the input devices which results in 3.8 mV offset and 3 mV kick-back noise.

An 8Gbps discrete time linear equalizer in 40nm CMOS technology

This paper introduces a new circuit technique for a discrete-time linear equalizer that can be used with current-integrating decision feedback equalizers. The DTLE samples and amplifies the input data in a clock phase then holds the output data in the other clock phase. The latter is the integrating phase of a current-integrating DFE. The DTLE is designed for a half-rate 8-Gbps serial-link receiver equalizer in 40-nm CMOS technology and draws 190-uW from a 1.1-V supply. The technique uses clocked current sources improving the power consumption.

A wideband 5 GHz digital PLL using a low-power two-step time-to-digital converter

This paper presents the design of a wideband, low-jitter 5 GHz digital phase-locked loop (DPLL) in 65 nm CMOS. The DPLL uses a high-resolution, low-power two-step time-to-digital converter (TDC) to achieve a wide loop bandwidth (BW) with low jitter. The DPLL is designed with a loop BW of 4 MHz using a 100 MHz reference and achieves a root mean square (RMS) jitter and a peak-to-peak (PP) jitter of 1.59 ps and 20.69 ps respectively at 5 GHz operation. The DPLL occupies an area of 0.026 mm2 and consumes 4.5 mA from a 1.2 V supply.