Farid Medjdoub

Low On-Resistance High-Breakdown Normally Off AlN/GaN/AlGaN DHFET on Si Substrate

Ultrathin-barrier normally off AlN/GaN/AlGaN double-heterostructure field-effect transistors using an in situ SiN cap layer have been fabricated on 100-mm Si substrates for the first time. The high 2DEG density in combination with an extremely thin barrier layer leads to enhancement-mode devices with state-of-the-art combination of specific on-resistance that is as low as 1.25 m¿·cm2 and breakdown voltage of 580 V at V GS = 0 V . Despite the 2-¿m gate length used, the transconductance peaks above 300 mS/mm. Furthermore, pulsed measurements show that the devices are dispersion free up to high drain voltage V DS = 50 V. More than 200 devices have been characterized in order to confirm the reproducibility of the results.

A comprehensive reliability investigation of the voltage-, temperature- and device geometry-dependence of the gate degradation on state-of-the-art GaN-on-Si HEMTs

In this work, the gate degradation of GaN-based HEMTs is analyzed. We find that the gate degradation does not occur only beyond a critical voltage, but it has a strong voltage accelerated kinetics and a weak temperature dependence. By means of a statistical study we show that the time-to-failure can be fitted best with a Weibull distribution. By using the distribution parameters and a power law model it is possible to perform lifetime extrapolation based on the gate degradation at a defined failure level and temperature for the first time. From this elaboration, the lifetime of a given device geometry can also be extracted. Eventually, the strong bias dependence of the gate degradation reported here implies that this phenomenon should be assessed by means of a voltage-based accelerated investigation as described in this work.

Low leakage high breakdown e-mode GaN DHFET on Si by selective removal of in-situ grown Si 3 N 4

We describe the fabrication and characteristics of high voltage enhancement mode SiN/AlGaN/GaN/AlGaN double heterostructure FET devices. The Si3N4 not only acts as a passivation layer but is crucial in the device concept as it acts as an electron donating layer (1). By selective removal under the gate of the in-situ SiN, we realize e-mode operation with a very narrow threshold voltage distribution with an average value of +475 mV and a standard deviation of only 15 mV. Compared to the reference depletion mode devices, we see no impact of the e-mode architecture on the breakdown behaviour. The devices maintain very low leakage currents even at drain biases up to 80% of the breakdown voltage.

Novel E-Mode GaN-on-Si MOSHEMT Using a Selective Thermal Oxidation

A novel normally-off AIN/GaN metal-oxide-semiconductor high electron mobility transistors (MOSHEMT) on 100-mm Si substrates for high-power applications is demonstrated for the first time by means of a selective thermal oxidation of AIN. The formation of a high-quality insulating AION layer resulting from the dry thermal oxidation of AIN at 900 °C in oxygen has been identified by transmission electron microscopy and X-ray photoelectron spectroscopy. The AIN thermal oxidation appears to be highly selective toward the SiN cap layer allowing the local depletion of the 2-D electron gas (self-aligned to the gate) and thus the achievement of normally-off operation. Threshold voltage (VT) of +0.8 V and drain leakage current at VGS = 0 V well below 1 μA/mm are obtained reproducibly over the wafer. The comparison of the fabricated MOSHEMTs with the control sample (identical but nonoxidized) reveals a drastic shift of VT toward positive values and three to four orders of magnitude drain leakage current reduction.

Excellent Stability of GaN-on-Si High Electron Mobility Transistors with 5 µm Gate–Drain Spacing Tested in Off-State at a Record Drain Voltage of 200 V and 200 °C

AlGaN/GaN high electron mobility transistors (HEMTs) were electrically stressed in pinch-off condition at a drain voltage up to 200 V for 200 h at an ambient temperature of 200 °C. The tested transistors which were grown and processed on 4-in. silicon substrate showed negligible degradation. This proves that a combination of a high quality AlGaN/GaN/AlGaN double heterostructure, the in-situ Si3N4 deposition technique and an accurately optimized gate technology result in excellent device stability under harsh conditions.

High temperature on- and off-state stress of GaN-on-Si HEMTs with in-situ Si 3 N 4 cap layer

In this work the stability of Gallium Nitride based high electron mobility transistors grown on 4-in Si substrate (GaN-on-Si HEMTs) were tested both in off-state at high drain voltage (200 V) and in on-state at large gate voltage (+2 V) with low drain bias (5 V). In each stress experiment the ambient temperature was fixed at 200°C. Remarkably, despite the considerably large drain voltage used in the off-state stress on only 5 μm gate-drain spaced transistors, negligible signs of degradation were observed after more than 350 hours of testing. Similar results were obtained after the on-state stress. In fact, only small degradation signs were reported in spite of the large gate current and high junction temperature the devices have to withstand during the on-state stress. These results show the robustness of these devices to operate under high electric field conditions, high temperature and to withstand also a large gate current for considerable time.

Preliminary reliability at 50 V of state-of-the-art RF power GaN-on-Si HEMTs

In this paper, state-of-the-art 1 mm RF power GaN-on-Si HEMTs using thick in-situ grown SiN cap layer are presented. Output power density POUT exceeding 10 W/mm is reproducibly achieved above 50 V drain voltage while still limited by thermal issues. In order to assess the device stability, the GaN-on-Si HEMTs have been tested at high channel temperature (> 300°C) and under high electric field (VDS = 50 V). The results demonstrate for the first time the possibility to combine extremely high RF output power density at VDS = 50 V with high reliability using a cost-effective technology.

GaN-on-Si power field effect transistors

GaN-on-Si has become the most promising technology for next-generation power switching devices to overcome intrinsic Si limits for high temperature operation, high efficiency at high operating voltage, and high switching frequency. Depletion-mode devices are already offering more than one order of magnitude lower specific on-resistance above 600V. Further, we have recently demonstrated e-mode devices (Vt>0.5V) with high current density, thanks to a unique in-situ SiN passivation approach. This in-situ SiN layer is further shown to be a key parameter for device stability at elevated temperatures, significantly enhancing the device reliability in high temperature accelerated lifetime tests.