K. Cheng

Improvement of AlGaN∕GaN high electron mobility transistor structures by in situ deposition of a Si3N4 surface layer

We have made AlGaN∕GaN high electron mobility transistors with a Si3N4 passivation layer that was deposited in situ in our metal-organic chemical-vapor deposition reactor in the same growth sequence as the rest of the layer stack. The Si3N4 is shown to be of high quality and stoichiometric in composition. It reduces the relaxation, cracking, and surface roughness of the AlGaN layer. It also neutralizes the charges at the top AlGaN interface, which leads to a higher two-dimensional electron-gas density. Moreover, it protects the surface during processing and improves the Ohmic source and drain contacts. This leads to devices with greatly improved characteristics.

Low On-Resistance High-Breakdown Normally Off AlN/GaN/AlGaN DHFET on Si Substrate

Ultrathin-barrier normally off AlN/GaN/AlGaN double-heterostructure field-effect transistors using an in situ SiN cap layer have been fabricated on 100-mm Si substrates for the first time. The high 2DEG density in combination with an extremely thin barrier layer leads to enhancement-mode devices with state-of-the-art combination of specific on-resistance that is as low as 1.25 m¿·cm2 and breakdown voltage of 580 V at V GS = 0 V . Despite the 2-¿m gate length used, the transconductance peaks above 300 mS/mm. Furthermore, pulsed measurements show that the devices are dispersion free up to high drain voltage V DS = 50 V. More than 200 devices have been characterized in order to confirm the reproducibility of the results.

AlGaN/GaN/AlGaN Double Heterostructures on Silicon Substrates for High Breakdown Voltage Field-Effect Transistors with low On-Resistance

AlGaN/GaN/AlGaN double heterostructure field-effect transistors (DHFET) with high breakdown voltage and low on-resistance were fabricated on silicon substrates. A linear dependency of the breakdown voltage on the buffer thickness and on the buffer Aluminium concentration was found. A breakdown voltage as high as 830 V and an on-resistance as low as 6.2 Ωmm were obtained in devices processed on 3.7 µm buffer thickness. The gate–drain spacing was 8 µm and the devices did not have any field plates.

A comprehensive reliability investigation of the voltage-, temperature- and device geometry-dependence of the gate degradation on state-of-the-art GaN-on-Si HEMTs

In this work, the gate degradation of GaN-based HEMTs is analyzed. We find that the gate degradation does not occur only beyond a critical voltage, but it has a strong voltage accelerated kinetics and a weak temperature dependence. By means of a statistical study we show that the time-to-failure can be fitted best with a Weibull distribution. By using the distribution parameters and a power law model it is possible to perform lifetime extrapolation based on the gate degradation at a defined failure level and temperature for the first time. From this elaboration, the lifetime of a given device geometry can also be extracted. Eventually, the strong bias dependence of the gate degradation reported here implies that this phenomenon should be assessed by means of a voltage-based accelerated investigation as described in this work.

A 96% Efficient High-Frequency DC–DC Converter Using E-Mode GaN DHFETs on Si

III-Nitride materials are very promising to be used in next-generation high-frequency power switching applications. In this letter, we demonstrate the performance of normally off AlGaN/GaN/AlGaN double-heterostructure FETs (DHFETs) using a boost-converter circuit. The figures of merit of our large (57.6-mm gate width) GaN transistor are presented: RON * QG of 2.5 Ω·nC is obtained at VDS = 140 V. The switching performance of the GaN DHFET is studied in a dedicated high-frequency boost converter: both the switching times and power losses are characterized. We show converter efficiency values up to 96.1% at 500 kHz and 93.9% at 850 kHz at output power of 100 W.

Growth of GaN on Ge(111) by molecular beam epitaxy

The epitaxial growth of GaN on Ge is reported. The authors found that direct growth of GaN performs exceptionally well on Ge(111) with plasma assisted molecular beam epitaxy. A streaky reflection high energy electron diffraction pattern is observed during growth. X-ray diffraction showed a rocking curve full width at half maximum of only 371arcsec for a 38nm GaN layer and indicates an abrupt interface between the GaN and Ge. Secondary ion mass spectrometry shows limited diffusion of Ga atoms into the Ge substrate and Ge atoms into the GaN layers. Current-voltage measurements show rectifying behavior for n-GaN on p-Ge. Their results indicate that GaN growth on Ge does not require intermediate layers, allowing the Ge substrate to be used as back contact in vertical devices. A p-n junction formed between GaN and Ge can be used in heterojunction devices.

Low leakage high breakdown e-mode GaN DHFET on Si by selective removal of in-situ grown Si 3 N 4

We describe the fabrication and characteristics of high voltage enhancement mode SiN/AlGaN/GaN/AlGaN double heterostructure FET devices. The Si3N4 not only acts as a passivation layer but is crucial in the device concept as it acts as an electron donating layer (1). By selective removal under the gate of the in-situ SiN, we realize e-mode operation with a very narrow threshold voltage distribution with an average value of +475 mV and a standard deviation of only 15 mV. Compared to the reference depletion mode devices, we see no impact of the e-mode architecture on the breakdown behaviour. The devices maintain very low leakage currents even at drain biases up to 80% of the breakdown voltage.

Novel E-Mode GaN-on-Si MOSHEMT Using a Selective Thermal Oxidation

A novel normally-off AIN/GaN metal-oxide-semiconductor high electron mobility transistors (MOSHEMT) on 100-mm Si substrates for high-power applications is demonstrated for the first time by means of a selective thermal oxidation of AIN. The formation of a high-quality insulating AION layer resulting from the dry thermal oxidation of AIN at 900 °C in oxygen has been identified by transmission electron microscopy and X-ray photoelectron spectroscopy. The AIN thermal oxidation appears to be highly selective toward the SiN cap layer allowing the local depletion of the 2-D electron gas (self-aligned to the gate) and thus the achievement of normally-off operation. Threshold voltage (VT) of +0.8 V and drain leakage current at VGS = 0 V well below 1 μA/mm are obtained reproducibly over the wafer. The comparison of the fabricated MOSHEMTs with the control sample (identical but nonoxidized) reveals a drastic shift of VT toward positive values and three to four orders of magnitude drain leakage current reduction.

Si Trench Around Drain (STAD) technology of GaN-DHFETs on Si substrate for boosting power performance

We report on the first measurement results to obtain over 2 kV breakdown voltage (VBD) of GaN-DHFETs on Si substrates by etching a Si Trench Around Drain contacts (STAD). Similar devices without trenches show VBD of only 650 V. DHFETs fabricated with STAD technology show excellent thermal performance confirmed by electrical measurements and finite element thermal simulations. We observe lower buffer leakage at high temperature (100°C) after STAD compared to devices with Si substrate, enabling high temperature device operation.

Mg doping of GaN by molecular beam epitaxy

We present a systematic study on the influence of growth conditions on the incorporation and activation of Mg in GaN layers grown by plasma-assisted molecular beam epitaxy. We show that high quality p-type GaN layers can be obtained on GaN-on-silicon templates. The Mg incorporation and the electrical properties have been investigated as a function of growth temperature, Ga?:?N flux ratio and Mg?:?Ga flux ratio. It was found that the incorporation of Mg and the electrical properties are highly sensitive to the Ga?:?N flux ratio. The highest hole mobility and lowest resistivity were achieved for slightly Ga-rich conditions. In addition to an optimal Ga?:?N ratio, an optimum Mg?:?Ga flux ratio was also observed at around 1%. We observed a clear Mg flux window for p-type doping of GaN?: 0.31% < Mg?:?Ga < 5.0%. A lowest resistivity of 0.98???cm was obtained for optimized growth conditions. The p-type GaN layer then showed a hole concentration of 4.3 ? 1017?cm?3 and a mobility of 15?cm2?V?1?s?1. Temperature-dependent Hall effect measurements indicate an acceptor depth in these samples of 100?meV for a hole concentration of 5.5 ? 1017?cm?3. The corresponding Mg concentration is 5 ? 1019?cm?3, indicating approximately 1% activation at room temperature. In addition to continuous growth of Mg-doped GaN layers we also investigated different modulated growth procedures. We show that a modulated growth procedure has only limited influence on Mg doping at a growth temperature of 800??C or higher. This result is thus in contrast to previously reported GaN?:?Mg doping at much lower growth temperatures of 500??C.