Farzin Karimi

Using data compression in automatic test equipment for system-on-chip testing

Compression has been used in automatic test equipment (ATE) to reduce storage and application time for high volume data by exploiting the repetitive nature of test vectors. The application of a binary compression method to an ATE environment for manufacturing is studied using a technique, referred to as reuse. In reuse, compression is achieved by partitioning the vector set and removing repeating segments. This process has O(n/sup 2/) time complexity for compression (where n is the number of vectors) with a simple hardware decoding circuitry. It is shown that for industrial system-on-chip (SoC) designs, the efficiency of the reuse compression technique is comparable to sophisticated software techniques with the advantage of easy and fast decoding. Two shift register-based decompression schemes are presented; they can be either incorporated into internal scan chains or built in the testers head. The proposed compression method has been applied to industrial test and data and an average compression rate of 84% has been achieved.

Data compression for system-on-chip testing using ATE

The manufacturing test of Systems-on-Chip (SoC) requires new design considerations for automatic test equipment (ATE). Compression has beers used in ATE to reduce storage and application time for high volume data by exploiting the repetitive nature of test vectors. Furthermore, the availability of boundary scan and the stringent integration requirements in the design of a head in an ATE necessitate a hardware-based technique which does not impact performance due to an excessive time complexity. The application of a binary compression method to an ATE environment for manufacturing test is studied using a technique, referred to as Reuse. In Reuse, compression is achieved by partitioning the vector set and removing repeating segments. This process has O(n/sup 2/) time complexity for compression (where n is the number of vectors) with a simple hardware decoding circuitry. It is shown that for industrial SoC designs; the efficiency of the Reuse compression technique is comparable with sophisticated software compression techniques with the advantage of easy and fast decoding (decoding is performed using shift registers which can be incorporated into the boundary scan or the head).

A scan-BIST environment for testing embedded memories

This paper presents a new IEEE 1149.1 compatible architecture as an intermediate environment for testing embedded memories. A BIST structure and a boundary scan are used for testing various memory configurations for programmability as well as improved controllability and observability. Its novelty is that features such as modularity, scalability with word size and adaptability to different memory configurations and testing requirements, are accomplished at relative ease. In the boundary scan, user-defined test modes are utilized so that basic modifications to the elements of a seed algorithm can be generated very efficiently.

A parallel approach for testing multi-port static random access memories

This paper presents a novel approach for testing multiport memories. This approach is based on the parallel execution of the testing process so that inter-port faults (shorts and coupling faults) can be detected at no loss of coverage and with no increase in the number of tests compared with a single-port memory. The parallelization is based on partitioning the memory into so-called segments. Test is completed in several phases. In each phase, the operation of a port is restricted to a segment. A port assignment process is utilized together with the partitioning of the memory; it considers the functionalities of the ports and their relation with respect to the addresses and the placement of the cells.

Parallel testing of multi-port static random access memories for BIST

Presents a built-in-self test (BIST) technique to implement the parallel approach for testing multi-port memories. This approach is based on the parallel execution of the testing process so that inter-port faults (shorts and coupling faults) can be detected at no loss of coverage and with no increase in the number of tests compared with a single-port memory. In the proposed hardware scheme, address data and control sequences are generated using a BIST controller originally designed for a single port memory; a simple logic unit is also used to interface the signals for BIST to the memory ports. It is shown that the proposed BIST implementation is O(N log N), where N is the number of ports.

Hybrid multisite testing at manufacturing

This paper deals with Hybrid multisite testing of VLSI chips by utilizing automatic test equipment (ATE) in connection with built-in self-test (BIST). The performance of a multisite testing process is analyzed using device-under-test (OUT) parameters (such as yield and average number of faults per DUT) as well as test process features (such as number of channels, coverage and touchdown time for the head). Two scenarios which permit immediate and delayed replacements, are considered and analytical models are given to establish the multisite test time of an ATE. A hybrid BIST and ATE approach is also analyzed to improve the performance of a multisite test environment and to better utilize the channels in the head of the tester.

Random testing of multi-port static random access memories

This paper presents the analysis and modeling of random testing for its application to multi-port memories. Ports operate to simultaneously test the memory and detecting multi-port related faults. The state of the memory under test in the presence of inter-port faults has been modeled using Markov state diagrams. In the state diagrams, transition probabilities are established by considering the effects of the memory operations (read and write), the lines involved in the fault (bit and word-lines) as well as the types and number of ports. Test lengths per cell at 99.9% coverage are given.

Fault detection in a tristate system environment

Embedded computers commonly rely on multiple-board systems, called tristate system environments. These environments consist of an interconnect and drivers or receivers with tristate features and boundary scan capabilities. The authors present a comprehensive fault model that provides 100 percent fault coverage and minimizes test set size.