Pramod Kolar

Process Technology Variation

Moores law technology scaling has improved performance by five orders of magnitude in the last four decades. As advanced technologies continue the pursuit of Moores law, a variety of challenges will need to be overcome. One of these challenges is the management of process variation. This paper discusses the importance of process variation in modern transistor technology, reviews front-end variation sources, presents device and circuit variation measurement techniques, including circuit and memory data from the 32-nm node, and compares recent intrinsic transistor variation performance from the literature.

A 32 nm High-k Metal Gate SRAM With Adaptive Dynamic Stability Enhancement for Low-Voltage Operation

SRAM bitcell design margin continues to shrink due to random and systematic process variation in scaled technologies and conventional SRAM faces a challenge in realizing the power and density benefits of technology scaling. Smart and adaptive assist circuits can improve design margins while satisfying SRAM power and performance requirements in scaled technologies. This paper introduces an adaptive, dynamic SRAM word-line under-drive (ADWLUD) scheme that uses a bitcell-based sensor to dynamically optimize the strength of WLUD for each die. The ADWLUD sensor enables 130 mV reduction in SRAM Vccmin while increasing frequency yield by 9% over conventional SRAM without WLUD. The sensor area overhead is limited to 0.02% and power overhead is 2% for a 3.4 Mb SRAM array.

A 1.1 GHz 12

A low-power, high-speed SRAM macro is designed in a 65 nm ultra-low-power (ULP) logic technology for mobile applications. The 65 nm strained silicon technology improves transistor performance/leakage tradeoff, which is essential to achieve fast SRAM access speed at substantially low operating voltage and standby leakage. The 1 Mb SRAM macro features a 0.667 mum2 low-leakage memory cell and can operate over a wide range of supply voltages from 1.2 V to 0.5 V. It achieves operating frequency of 1.1 GHz and 250 MHz at 1.2 V and 0.7 V, respectively. The SRAM leakage is reduced to 12 muA/Mb at the data retention voltage of 0.5 V. The measured bitcell leakage from the SRAM array is ~2 pA/bit at retention voltage with integrated leakage reduction schemes.

\mu

CMOS technology has followed Moores law into the nanoscale regime where SRAM scaling is facing increasing challenges in gaining performance at reduced leakage power for future product applications. Despite the advances in process technologies and the resultant ability to produce ever-smaller feature sizes, the increasing variations of scaled devices in SRAM are playing an increasingly important role in determining the scaling of SRAM operating voltage (VCC), frequency and leakage power. We develop a high-performance voltage-scalable SRAM design in 32nm logic CMOS featuring 2nd-generation high-κ metal-gate transistors and 4th-generation strained silicon [1]. With the continued transistor performance enhancement and extensive process-circuit co-optimization, the 32nm SRAM design is able to achieve 2× improvement in density and 15% faster access speed when compared to the 45nm design [2] at the same voltage. The design supports a broad range of operating voltages to enable dynamic voltage scaling in todays high-performance and low-power applications. The design also features an integrated power management scheme with close-loop array leakage control, floating bitline and wordline driver sleep, resulting in 58% reduction of SRAM leakage consumption.

A/Mb-Leakage SRAM Design in 65 nm Ultra-Low-Power CMOS Technology With Integrated Leakage Reduction for Mobile Applications

Six-transistor SRAM cells have served as the workhorse embedded memory for several decades. However, with aggressive technology scaling, designers find it increasingly difficult to guarantee robust operation at low voltages because of the worsening process variation. This article presents circuit techniques pursued by industry to overcome SRAM scaling challenges in future technology nodes.

A 4.0 GHz 291Mb voltage-scalable SRAM design in 32nm high-κ metal-gate CMOS with integrated power management

A simulation based pre-silicon leakage estimation methodology for SRAM is proposed. The methodology is easily extended to different voltage and temperature corners and it enables determination of leakage yield. It comprehends the impact of die to die and within die variations. It is used to generate yield specific leakage multipliers to capture impact of variability on leakage. Comparative studies between different bit cells show that relative leakage could be up to 53% different if we do not use the methodology. Finally, results from the methodology are shown to match measured silicon data at 22nm tri-gate CMOS technology within 12% accuracy over the region of interest.