Felipe de Souza Marques

DAG based library-free technology mapping

This paper proposes a library-free technology mapping algorithm to reduce delay in combinational circuits. The algorithm reduces the overall number of series transistors through the longest path, considering that each cell network has to obey to a maximum admitted chain. The number of series transistors is computed in a Boolean way, reducing the structural bias. The mapping algorithm is performed on a Directed Acyclic Graph (DAG) description of the circuit. Preliminary results for delay were obtained through SPICE simulations. When compared to the SIS technology mapping, the proposed method shows significant delay reductions, considering circuits mapped with different libraries.

KL-cuts: a new approach for logic synthesis targeting multiple output blocks

This paper introduces the concept of kl-feasible cuts, by controlling both the number k of inputs and the number l of outputs in a circuit cut. To provide scalability, the concept of factor cuts is extended to kl-cuts. Algorithms for computing this kind of cuts, including kl-cuts with unbounded k, are presented and results are shown. As a practical application, a covering algorithm using these cuts is presented.

A comparative study of CMOS gates with minimum transistor stacks

The performance of CMOS gates is strongly dependent on the number of transistors in series in both pull-up PMOS and pull-down NMOS networks. In this paper, two approaches presenting the minimum number of stacked devices are compared, using conventional series-parallel CMOS as a reference. The proposed analysis takes into consideration different lists of cells, including standard cell libraries used in regular (fixed library) technology mapping or functions generated by software in library-free technology mapping. The quality of the transistor networks in consideration is evaluated according to device count, worst case transistor stack, as well as logical effort of the network. The relationship between such topologies and technology mapping is also discussed.

Fast disjoint transistor networks from BDDs

In this paper, we describe different ways to derive transistor networks from BDDs. The use of disjoint pull-up (composed of PMOS transistors) and pull-down (composed of NMOS transistors) planes allows simplifications that result in shorter pull-up and pull-down transistor stacks. The reduced length of transistor stacks leads to the fastest implementation among the six different strategies evaluated to generate transistor networks from BDDs. Delay and area results are presented showing the impact of the proposed strategy.

Graph-Based Transistor Network Generation Method for Supergate Design

Transistor network optimization represents an effective way of improving VLSI circuits. This paper proposes a novel method to automatically generate networks with minimal transistor count, starting from an irredundant sum-of-products expression as the input. The method is able to deliver both series-parallel (SP) and non-SP switch arrangements, improving speed, power dissipation, and area of CMOS gates. Experimental results demonstrate expected gains in comparison with related approaches.

SwitchCraft: a framework for transistor network design

SwitchCraft framework provides a set of tools for switch network and logic gate generation. Switch networks corresponding to logic functions can be generated from Boolean expressions and from BDD. Logically and topologically complementary networks can be derived through dual-graphs. Different CMOS logic styles can be obtained, e.g. single- and dual-rail, static and dynamic topologies, with disjoint planes and in PTL-like structure (with shared pull-up/pull-down structures). Estimators for delay propagation, layout area and power dissipation (dynamic and leakage components) are available. The switch network profile can also be extracted, providing the logic function behavior, switch/transistor count, number of connections in intra-cell nodes, the longest and shortest paths, and so on.

A new approach to the use of satisfiability in false path detection

This paper presents a novel method for false path detection using satisfiability. It is based on circuit node properties that are related to non-testable stuck-at faults as well as to false path detection. When compared to traditional satisfiability methods that generate sat instances associated to paths, the proposed method is more efficient. This efficiency derives from the fact that most digital circuits have a number of nodes that is smaller than the number of paths.

Topological characteristics of logic networks generated by a graph-based methodology

Graph-based methodologies for supergate design have gained relevance recently. Due to the non-series-parallel arrangements and the transistor sharing technique, these methodologies can deliver a network with fewer transistors, leading to an efficient logic design. However, through its optimization processes, these methods introduces some topology particularities in the logic network, which impacts directly in the layout. This paper presents a methodology to identify these aspects in order to guide the cell layout generation. The results were performed over a set of intensively used benchmarks and pointed that 67.69% of the investigated networks presents a planar topology, while 21.85% shows a different number of transistors between its logic plans and 93.73% of the physical cells will contain at least one gap in its diffusion areas.

Evaluating Geometric Aspects of Non-Series-Parallel Cells

Recent works demonstrate constant optimizations in the number of transistors necessary to implement some logic functions by using non-series-parallel arrangements. However, these kind of networks can produce non-dual and non-planar structures, which cannot be fully treated by some of the classical algorithms dedicated to placement. In this paper we present two methodologies to place and route non-series-parallel cells, providing useful methods to estimate area and wirelength. These methods can also be applied in series-parallel topologies. The experiments performed in this paper show an effectively optimization on non-series-parallel layouts.

Improving the methodology to build non-series-parallel transistor arrangements

This paper presents an improvement in our previous methodology to generate efficient transistor networks. The proposed method applies graph-based optimizations and is capable to deliver series-parallel and non-series-parallel arrangements with reduced transistor count. The main feature of our methodology is the possibility to avoid greedy choices during the beginning of the optimization process. This property is associated to an edges compression technique that also contributes to minimize the bad effect of the greedy choices. Performed experiments have demonstrated the efficiency of this methodology when comparing to other available techniques.