Leomar Soares da Rosa

DAG based library-free technology mapping

This paper proposes a library-free technology mapping algorithm to reduce delay in combinational circuits. The algorithm reduces the overall number of series transistors through the longest path, considering that each cell network has to obey to a maximum admitted chain. The number of series transistors is computed in a Boolean way, reducing the structural bias. The mapping algorithm is performed on a Directed Acyclic Graph (DAG) description of the circuit. Preliminary results for delay were obtained through SPICE simulations. When compared to the SIS technology mapping, the proposed method shows significant delay reductions, considering circuits mapped with different libraries.

A comparative study of CMOS gates with minimum transistor stacks

The performance of CMOS gates is strongly dependent on the number of transistors in series in both pull-up PMOS and pull-down NMOS networks. In this paper, two approaches presenting the minimum number of stacked devices are compared, using conventional series-parallel CMOS as a reference. The proposed analysis takes into consideration different lists of cells, including standard cell libraries used in regular (fixed library) technology mapping or functions generated by software in library-free technology mapping. The quality of the transistor networks in consideration is evaluated according to device count, worst case transistor stack, as well as logical effort of the network. The relationship between such topologies and technology mapping is also discussed.

Graph-Based Transistor Network Generation Method for Supergate Design

Transistor network optimization represents an effective way of improving VLSI circuits. This paper proposes a novel method to automatically generate networks with minimal transistor count, starting from an irredundant sum-of-products expression as the input. The method is able to deliver both series-parallel (SP) and non-SP switch arrangements, improving speed, power dissipation, and area of CMOS gates. Experimental results demonstrate expected gains in comparison with related approaches.

SwitchCraft: a framework for transistor network design

SwitchCraft framework provides a set of tools for switch network and logic gate generation. Switch networks corresponding to logic functions can be generated from Boolean expressions and from BDD. Logically and topologically complementary networks can be derived through dual-graphs. Different CMOS logic styles can be obtained, e.g. single- and dual-rail, static and dynamic topologies, with disjoint planes and in PTL-like structure (with shared pull-up/pull-down structures). Estimators for delay propagation, layout area and power dissipation (dynamic and leakage components) are available. The switch network profile can also be extracted, providing the logic function behavior, switch/transistor count, number of connections in intra-cell nodes, the longest and shortest paths, and so on.

Topological characteristics of logic networks generated by a graph-based methodology

Graph-based methodologies for supergate design have gained relevance recently. Due to the non-series-parallel arrangements and the transistor sharing technique, these methodologies can deliver a network with fewer transistors, leading to an efficient logic design. However, through its optimization processes, these methods introduces some topology particularities in the logic network, which impacts directly in the layout. This paper presents a methodology to identify these aspects in order to guide the cell layout generation. The results were performed over a set of intensively used benchmarks and pointed that 67.69% of the investigated networks presents a planar topology, while 21.85% shows a different number of transistors between its logic plans and 93.73% of the physical cells will contain at least one gap in its diffusion areas.

Evaluating Geometric Aspects of Non-Series-Parallel Cells

Recent works demonstrate constant optimizations in the number of transistors necessary to implement some logic functions by using non-series-parallel arrangements. However, these kind of networks can produce non-dual and non-planar structures, which cannot be fully treated by some of the classical algorithms dedicated to placement. In this paper we present two methodologies to place and route non-series-parallel cells, providing useful methods to estimate area and wirelength. These methods can also be applied in series-parallel topologies. The experiments performed in this paper show an effectively optimization on non-series-parallel layouts.

Speed-Up of ASICs Derived from FPGAs by Transistor Network Synthesis Including Reordering

This paper presents a method for speeding-up ASICs by transistor reordering. The proposed method can be applied to a variety of logic styles and transistor topologies. The rationale of the obtained gains is explained through logical effort concepts. When applied to circuits based on 4-input networks, which is the case of many structured-ASIC or FPGA technologies, significant performance gains are obtained at a small area expense. This observation points out that our method can be of special interest when migrating FPGAs to ASICs. The logical effort effects on networks derived from BDDs illustrated in this paper can be exploited in a much broader range of designs.

Transistor placement strategies for non-series-parallel cells

Regarding optimized logic network generation, recent papers have demonstrated that non-series-parallel topologies can deliver arrangements with fewer transistors when compared to the widely used series-parallel approach. However, due to its topology particularities, this paradigm represents a challenge for physical cell design, especially concerning the transistor placement procedure. In this scenario, we present an analysis of two divergent placement strategies: the first based on a continuous active area approach, aiming to produce cells with minimized diffusion gaps, and the second based on a continuous polysilicon gates paradigm, where the target is to maximize the vertical gates alignment. In order to evaluate both placement policies regarding geometrical and electrical aspects, we performed experiments in a well-known benchmark. The continuous polysilicon gates strategy presented optimizations in the cell area, wirelength, input capacitance, leakage, internal and switching power, while the continuous active area strategy showed better results concerning propagation and transition delay. These results can be used as a guide to an adaptive placement methodology implemented in automatic layout design tools to deal with non-series-parallel arrangements.

Transistor Count Optimization in IG FinFET Network Design

Double-gate devices, like independent-gate (IG) FinFET, have introduced new possibilities and challenges in synthesis of transistor networks. Existing factorization methods and graph-based optimizations are not actually the most effective way to generate optimized IG FinFET based networks because only reducing the number of literals in a given Boolean expression does not guarantee the minimum transistor count. This paper presents two novel methods aiming the minimization of the number of devices in logic networks. The first contribution is a method for defactoring Boolean expressions able to apply the conventional factorization algorithms together with IG FinFET particularities, so improving it. The second contribution is a novel graph-based method that improves even more transistor arrangements by exploiting enhanced nonseries-parallel associations. Experimental results shown a significant reduction in the size of transistor networks delivered by the proposed methods.

A parallel motion estimation solution for heterogeneous system on chip

This paper presents a parallel Motion Estimation (ME) solution for video coding on heterogeneous System-On-Chip (SoC), with two Implementation Versions: an OpenCL-based version targeting embedded GPGPUs and a hardware design targeting an embedded FPGA device. The current work considers a heterogeneous SoC composed of a variety distinct processing units such as CPU, DSP, Memory, GPGPU, and FPGA, where the FPGA component has support for dynamic reconfiguration. These two versions implement a parallelism-oriented algorithm and provide two performance/energy operation points allowing flexibility for dynamic power management according to runtime scenarios. The solution presented in this paper uses a scheme to reduce the number of operations required to perform the Sum of Absolute Differences (SAD) for the evaluated candidate blocks. This scheme is based on the accumulation of previously calculated SADs, considering the 8×8 Prediction Unities (PU) as base blocks, to generate the SAD for larger PUs. The proposed solution was evaluated in two platforms, (1) an Odroid XU-3, with a Samsung Exynos 5422 SoC, featuring a 64-core Mali-T628 MP6 GPGPU, and (2) an FPGA device. The performance and energy consumption results shows the FPGA implementation are able to process 49 HD 1080p fps with 1000× increased in energy efficiency when compared to the GPGPU implementation.