Vinicius Neves Possani

Graph-Based Transistor Network Generation Method for Supergate Design

Transistor network optimization represents an effective way of improving VLSI circuits. This paper proposes a novel method to automatically generate networks with minimal transistor count, starting from an irredundant sum-of-products expression as the input. The method is able to deliver both series-parallel (SP) and non-SP switch arrangements, improving speed, power dissipation, and area of CMOS gates. Experimental results demonstrate expected gains in comparison with related approaches.

Improving the methodology to build non-series-parallel transistor arrangements

This paper presents an improvement in our previous methodology to generate efficient transistor networks. The proposed method applies graph-based optimizations and is capable to deliver series-parallel and non-series-parallel arrangements with reduced transistor count. The main feature of our methodology is the possibility to avoid greedy choices during the beginning of the optimization process. This property is associated to an edges compression technique that also contributes to minimize the bad effect of the greedy choices. Performed experiments have demonstrated the efficiency of this methodology when comparing to other available techniques.

Transistor-level optimization of CMOS complex gates

This paper presents a new methodology to generate efficient transistor networks. Transistor-level optimization consists in an effective possibility to increase design quality when generating CMOS logic gates to be inserted in standard cell libraries. Starting from an input ISOP, the proposed method is able to deliver series-parallel and non-series-parallel arrangements with reduced transistor count. The experiments performed over the set of 4-input P-class Booleans functions have demonstrated the efficiency of the proposed approach.

Exploring Independent Gates in FinFET-Based Transistor Network Generation

This paper shows that double gate devices, like independent-gate (IG) FinFETs, have introduced new challenges in the transistor network generation step during the logic synthesis. The main point is that reducing the number of literals in a given Boolean expression is not enough to guarantee a minimum IG FinFET network implementation. This way, traditional factorization methods or graph-based optimizations may not be useful to generate networks for double gate devices. In this sense, this paper presents a graph-based method able to find promising arrangements to explore the separated gates of each IG FinFET. The experiments demonstrate that the proposed method can reduce the number of IG FinFETs compared to the traditional methods of transistor network generation.

Efficient transistor-level design of CMOS gates

The transistor arrangement optimization is an effective possibility to improve VLSI design, especially when generating CMOS logic gates to be inserted in standard cell libraries. This paper addresses this issue and presents a new methodology to generate efficient transistor networks. Starting from an input ISOP, the proposed method is capable to deliver series-parallel and non-series-parallel arrangements with reduced transistor count. By applying the proposed approach, it is possible to achieve optimized transistor arrangements since greedy choices are avoided during part of the generation process. The performed experiments have demonstrated the efficiency of this methodology when comparing to other available techniques.

Binary adder circuit design using emerging MIGFET devices

Multiple independent-gate field effect transistors (MIGFETs) have great potential for digital integrated circuits. In this work, we demonstrate that conventional binary adder architectures may benefit from the use of MIGFET devices. As case studies, we have designed ripple-carry adders (RCA) and parallel-prefix adders (PPA), where circuit area and performance optimizations are explored. Different versions of adders have been built using MIGFET and compared to adder topologies based on single-gate transistors.

Transistor Count Optimization in IG FinFET Network Design

Double-gate devices, like independent-gate (IG) FinFET, have introduced new possibilities and challenges in synthesis of transistor networks. Existing factorization methods and graph-based optimizations are not actually the most effective way to generate optimized IG FinFET based networks because only reducing the number of literals in a given Boolean expression does not guarantee the minimum transistor count. This paper presents two novel methods aiming the minimization of the number of devices in logic networks. The first contribution is a method for defactoring Boolean expressions able to apply the conventional factorization algorithms together with IG FinFET particularities, so improving it. The second contribution is a novel graph-based method that improves even more transistor arrangements by exploiting enhanced nonseries-parallel associations. Experimental results shown a significant reduction in the size of transistor networks delivered by the proposed methods.

Performance evaluation of optimized transistor networks built using independent-gate FinFET

MOS planar technology has been used in fabrication of integrated circuits in the last decades. However, the short channel effects in the subthreshold operation region are becoming a critical restriction to the channel length reduction. With the use of FinFET devices, the scaling increases due the reduction of short channel effects. FinFET offers the possibility of independent gate controlling that can be efficiently exploited in logic reduction (network optimization), but with direct impact in the electrical performance of logic gates. In this work, it is presented the electrical analysis in terms of signal delay propagation and energy consumption of compacted transistor networks. Different logic gate implementations corresponding to the same Boolean function behavior are compared. The results demonstrate the existing tradeoff between these two parameters.