Vinicius Callegaro

Graph-Based Transistor Network Generation Method for Supergate Design

Transistor network optimization represents an effective way of improving VLSI circuits. This paper proposes a novel method to automatically generate networks with minimal transistor count, starting from an irredundant sum-of-products expression as the input. The method is able to deliver both series-parallel (SP) and non-SP switch arrangements, improving speed, power dissipation, and area of CMOS gates. Experimental results demonstrate expected gains in comparison with related approaches.

Efficient method to compute minimum decision chains of Boolean functions

Every Boolean function has a unique property called Minimum Decision Chain (MDC). This paper proposes an effective way to compute this property for arbitrary functions. The proposed method is very efficient when compared to a more direct and intuitive approach, that is used as the reference for performance analysis. Different examples have been evaluated, and the results are discussed. The proposed method is able to compute the MDC value in order of milliseconds, allowing the use of MDC computation to guide logic synthesis algorithms.

Contributions to the evaluation of ensembles of combinational logic gates

This work presents an effective way for evaluating and validating ensembles of combinational CMOS gates and logic cell libraries. The major contributions include an innovative design methodology for such a kind of test vehicle, as well as a simple and flexible multi-operating mode circuit architecture. The resulting circuit is quite useful for cell library verification at different levels: in the EDA environment and on silicon prototyping. The proposed methodology can be applied for analysis taking into account the logic gate functionality, timing performance, power consumption and circuit operating impact of nanometer aging effects. Simulation results demonstrate the circuit operation, features and facilities described herein.

SwitchCraft: a framework for transistor network design

SwitchCraft framework provides a set of tools for switch network and logic gate generation. Switch networks corresponding to logic functions can be generated from Boolean expressions and from BDD. Logically and topologically complementary networks can be derived through dual-graphs. Different CMOS logic styles can be obtained, e.g. single- and dual-rail, static and dynamic topologies, with disjoint planes and in PTL-like structure (with shared pull-up/pull-down structures). Estimators for delay propagation, layout area and power dissipation (dynamic and leakage components) are available. The switch network profile can also be extracted, providing the logic function behavior, switch/transistor count, number of connections in intra-cell nodes, the longest and shortest paths, and so on.

SOP based logic synthesis for memristive IMPLY stateful logic

This work presents an efficient algorithm to obtain a material implication (IMPLY) expression from a sum-of-products (SOP). The resulting expression is computable with two work memristors. The proposed method has linear time complexity with respect to the SOP size. Comparison to previous work shows a reduction on the average number of IMPLY operations when applying the proposed method.

Transistor-level optimization of CMOS complex gates

This paper presents a new methodology to generate efficient transistor networks. Transistor-level optimization consists in an effective possibility to increase design quality when generating CMOS logic gates to be inserted in standard cell libraries. Starting from an input ISOP, the proposed method is able to deliver series-parallel and non-series-parallel arrangements with reduced transistor count. The experiments performed over the set of 4-input P-class Booleans functions have demonstrated the efficiency of the proposed approach.

Area impact analysis of via-configurable regular fabric for digital integrated circuit design

Transistor regular layout (TRL) has been considered a more lithography-reliable approach for digital integrated circuit design than the most conventional standard cell design. However, the impact in circuit area seems to be unavoidable due to the loss in design flexibility. Hence, the decision in applying such design strategy depends not only on the expected yield improvement but also on the careful evaluation of circuit penalty. This paper presents an extensive analysis and discussion about area impact of TRL design style in comparison to the standard cell one. Several benchmark circuits were mapped by addressing specific cell libraries built for this purpose. Experimental results demonstrated that efficient TRL templates may minimize significantly the area overhead.

Factored Forms for Memristive Material Implication Stateful Logic

This paper proposes the utilization of factored forms in logic synthesis for memristive material implication stateful logic. Factored forms have not been explored by previous works due to expected increasing on device count. We present an algorithm to obtain factored forms computable with minimum number of memristors. Comparison to previous works shows an average reduction of 12% in the number of operations to compute 4-input Boolean functions.

Iterative remapping respecting timing constraints

This paper proposes a novel iterative remapping approach for area reduction while still respecting the timing constraints of the design specification. The use of complex gates can potentially reduce cell area, but they have to be chosen wisely to preserve timing constraints while remapping. Commercial tools for logic synthesis work better with simple cells and are not fully capable of taking advantage of complex cells; the strategy proposed herein is aimed to better exploit complex cells during technology mapping. The proposed iterative remapping approach can exploit a larger amount of logic gates, reducing global circuit area and respecting global timing constraints. Experiments show area improvement of 8% on average and up to 15% for a subset of combinational mapped circuits of IWLS 2005 benchmarks.

Majority-based logic synthesis for nanometric technologies

Majority-based logic has received considerable attention due to emergent technologies that use the majority function as basic operation. As a consequence, the design of digital circuits using the majority-based logic has also been considered. Existing works essentially proposed different cell libraries to be applied in logic synthesis. However, the comparison between different approaches may not be straightforward since distinct circuit synthesis methodologies may be exploited. In order to allow a fair comparison of methodologies of generating quantum cellular automata (QCA) cell libraries and for performing QCA circuit synthesis is presented. The proposed library generation methodology is generic enough so that different basic logic functions can be considered. In addition to previous considered libraries, this work also considers a library comprising all 3-input functions implemented using both majority and AND-OR-Inverter gates. Experimental results compare different QCA libraries, showing that considering different basic gates leads to an average area reduction of up to 47%.