Felipe S. Marranghello

Impact and optimization of lithography-aware regular layout in digital circuit design

Regular fabrics are expected to mitigate manufacturing process variations, increasing fabrication yield in deep sub-micron CMOS technologies. This paper presents an extensive analysis of aspects involved in the optimization of regular fabric (based) designs. The choice of the most efficient regular fabric design strategy depends on the area overhead and circuit performance degradation, which may vary according the fabric pattern optimization possibilities. Yield improvements have to be traded-off against area and performance losses due to regular design rules. This paper evaluates the losses introduced by using regular fabrics. Several benchmark circuits have been mapped over different regular layout templates through specific cell libraries built for this purpose. Results have demonstrated that the design impact is quite manageable by choosing appropriately the fabric pattern or template.

Spin diode network synthesis using functional composition

This paper proposes an algorithm to synthesize combinational circuits based on spin diode logic technology. Spin diode is a magnetoresistive semiconductor heterojunction device which allows for a binary current based logic. The proposed algorithm takes the advantages of the functional composition (FC) approach to obtain fanout free network implementations with the minimum number of spin diodes. Experimental results have shown that the new proposal obtains better results when compared to the state-of-the-art algorithms that focus on traditional CMOS technology adapted to this new approach.

SOP based logic synthesis for memristive IMPLY stateful logic

This work presents an efficient algorithm to obtain a material implication (IMPLY) expression from a sum-of-products (SOP). The resulting expression is computable with two work memristors. The proposed method has linear time complexity with respect to the SOP size. Comparison to previous work shows a reduction on the average number of IMPLY operations when applying the proposed method.

Factored Forms for Memristive Material Implication Stateful Logic

This paper proposes the utilization of factored forms in logic synthesis for memristive material implication stateful logic. Factored forms have not been explored by previous works due to expected increasing on device count. We present an algorithm to obtain factored forms computable with minimum number of memristors. Comparison to previous works shows an average reduction of 12% in the number of operations to compute 4-input Boolean functions.

CMOS inverter delay model based on DC transfer curve for slow input

This work presents a novel approach to estimate the CMOS inverter delay. The proposed delay model uses the DC transfer curve in order to predict the inverter behavior for slow input transitions rather than estimating the discharging time. Moreover, the only required empirical parameters are those used to calibrate the transistor model. Results are on very good agreement with HSPICE simulations based on BSIM4 transistor model, over a wide range of input slopes and output loads. Comparisons to previously works show that such new delay model offers improved modeling with good trade-off between simplicity and accuracy. The average error is near to 3%, and the worst case error is smaller than 10%.

Majority-based logic synthesis for nanometric technologies

Majority-based logic has received considerable attention due to emergent technologies that use the majority function as basic operation. As a consequence, the design of digital circuits using the majority-based logic has also been considered. Existing works essentially proposed different cell libraries to be applied in logic synthesis. However, the comparison between different approaches may not be straightforward since distinct circuit synthesis methodologies may be exploited. In order to allow a fair comparison of methodologies of generating quantum cellular automata (QCA) cell libraries and for performing QCA circuit synthesis is presented. The proposed library generation methodology is generic enough so that different basic logic functions can be considered. In addition to previous considered libraries, this work also considers a library comprising all 3-input functions implemented using both majority and AND-OR-Inverter gates. Experimental results compare different QCA libraries, showing that considering different basic gates leads to an average area reduction of up to 47%.

Design-oriented delay model for CMOS inverter

This paper presents a new design oriented model for estimating the delay of a CMOS inverter. The model considers the impact of input transition time, input-to-output coupling capacitance, and physical effects such as drain-induced barrier lowering (DIBL) and velocity saturation. Thus, it is quite suitable for nanometer technologies. Moreover, no fitting parameters are required. Results are in very good agreement with HSPICE simulations based on BSIM4 transistor model over a wide range of input slopes and output loads, considering different inverter configurations. An average error of 3% in correlation to HSPICE has been attained.

Binary adder circuit design using emerging MIGFET devices

Multiple independent-gate field effect transistors (MIGFETs) have great potential for digital integrated circuits. In this work, we demonstrate that conventional binary adder architectures may benefit from the use of MIGFET devices. As case studies, we have designed ripple-carry adders (RCA) and parallel-prefix adders (PPA), where circuit area and performance optimizations are explored. Different versions of adders have been built using MIGFET and compared to adder topologies based on single-gate transistors.

SAT-Based Formulation for Logical Capacity Evaluation of VIA-Configurable Structured ASIC

This paper proposes a SAT-based formulation to evaluate the logical capacity of VIA-configurable block templates. The proposed solution is able to support any user-defined regular layout. The proposed SAT formulation was sucessufully applied to the three main VCSA fabrics in the literature considering transistor networks from an open cell library and transistor networks representing all 4-input Boolean functions. We observed that the number of literals and variables in the SAT formulation grows nearly quadratically with respect to the number of transistors in the VCSA fabric. We also noticed that the average runtime of the SAT solver presents a strong dependence on the input VCSA fabric.

Performance evaluation of optimized transistor networks built using independent-gate FinFET

MOS planar technology has been used in fabrication of integrated circuits in the last decades. However, the short channel effects in the subthreshold operation region are becoming a critical restriction to the channel length reduction. With the use of FinFET devices, the scaling increases due the reduction of short channel effects. FinFET offers the possibility of independent gate controlling that can be efficiently exploited in logic reduction (network optimization), but with direct impact in the electrical performance of logic gates. In this work, it is presented the electrical analysis in terms of signal delay propagation and energy consumption of compacted transistor networks. Different logic gate implementations corresponding to the same Boolean function behavior are compared. The results demonstrate the existing tradeoff between these two parameters.