Mayler G. A. Martins

Open Cell Library in 15nm FreePDK Technology

This paper presents the 15nm FinFET-based Open Cell Library (OCL) and describes the challenges in the methodology while designing a standard cell library for such advanced technology node. The 15nm OCL is based on a generic predictive state-of-the-art technology node. The proposed cell library is intended to provide access to advanced technology node for universities and other research institutions, in order to design digital integrated circuits and also to develop cell-based design flows, EDA tools and associated algorithms. Developing a 15nm standard cell library brings out design challenges which are not present in previous technology nodes. Some of these challenges include double-patterning for both metal and poly layers, a very restrictive set of physical design rules, and the demand for lithography-friendly patterns. This paper discusses the development of the library considering the challenges associated with advanced technology nodes.

Boolean factoring with multi-objective goals

This paper introduces a new algorithm for Boolean factoring. The proposed approach is based on a novel synthesis paradigm, functional composition, which performs synthesis by associating simpler sub-solutions with minimum costs. The method constructively controls characteristics of final and intermediate functions, allowing the adoption of secondary criteria other than the number of literals for optimization. This multi-objective factoring algorithm presents interesting features and advantages when compared to previous works.

Functional composition: A new paradigm for performing logic synthesis

This paper presents the functional composition (FC), a new paradigm for combinational logic synthesis. FC is based on the following principles: (1) representation of logic functions as a bonded pair of functional/structural representations; (2) it starts from a set of initial functions; (3) simpler functions are associated to create more complex ones; (4) a partial order that enables dynamic programming is respected; (5) a set of allowed functions is maintained to reduce execution time/memory consumption. We present functional composition algorithms variants for Boolean factoring, AIG rewriting, minimum decision chain computation and SOP generation.

Semi-custom NCL Design with Commercial EDA Frameworks: Is it Possible?

Quasi delay-insensitive design is a promising solution for coping with contemporary silicon technology problems such as aggressive process variations and tight power budgets. However, one major barrier to its wider adoption is the lack of automated optimization techniques for building circuits using semi-custom methodologies. This paper proposes an innovative design flow that relies on the use of consolidated commercial EDA frameworks for synthesizing 1-of-n 4-phase quasi delay-insensitive circuits using Null Convention Logic. Asynchronous gates that are usually not supported by these frameworks are modelled as conventional logic gates, allowing synthesis tools to perform static timing analysis as well as pre- and post-mapped design optimizations, which can be specified by the designer using conventional timing constraints.

Methodology for achieving best trade-off of area and fault masking coverage in ATMR

The use of Triple Modular Redundancy (TMR) with majority voters can guarantee full single fault masking coverage for a given circuit against transient faults. However, it presents a minimum area overhead of 200% compared to the original circuit. In order to reduce area overhead without compromising significantly the fault coverage, TMR can use approximated circuits approach to generate redundant modules that are optimized in area compared to the original module. Initial studies of this technique have shown that it is possible to reach a good balance between fault coverage and area overhead cost. In this work, we do a further analysis of this approach by using a new method to compute approximate functions and to select the best combinations of approximate circuits targeting the highest fault coverage. We use complex gates and employ structural reorder techniques. All the tests are done using a fault injection tool designed specifically for approximate TMR scheme. Results show that area overhead can be reduced greatly from 200% to 120%and still reaching fault coverage of more than 95%.

Synthesis of threshold logic gates to nanoelectronics

In this paper, a novel method to identify threshold logic functions (TLF) is proposed. Threshold logic is a promising alternative to conventional Boolean logic that has been recently revisited due to the suitability to emerging technologies, such as QCA, RTD, SET, TPL and spintronics. Identification and synthesis of TLF are fundamental tasks for the development of circuit design flow based on such logic style. The proposed method exploits both the order of Chow parameters and the system of inequalities, extracted from a function, to assign optimal variable weights and optimal threshold value. It is the first heuristic algorithm that does not uses integer linear programming (ILP) able to identify all threshold functions with up to five variables. Moreover, it also identifies more functions than other related heuristic methods when the number of variables is higher than five. The proposed algorithm is scalable, since the average execution time is less than 1 ms per function. Furthermore, the method always assigns the minimum weights, resulting in circuits with minimum area.

Efficient method to compute minimum decision chains of Boolean functions

Every Boolean function has a unique property called Minimum Decision Chain (MDC). This paper proposes an effective way to compute this property for arbitrary functions. The proposed method is very efficient when compared to a more direct and intuitive approach, that is used as the reference for performance analysis. Different examples have been evaluated, and the results are discussed. The proposed method is able to compute the MDC value in order of milliseconds, allowing the use of MDC computation to guide logic synthesis algorithms.

Spin diode network synthesis using functional composition

This paper proposes an algorithm to synthesize combinational circuits based on spin diode logic technology. Spin diode is a magnetoresistive semiconductor heterojunction device which allows for a binary current based logic. The proposed algorithm takes the advantages of the functional composition (FC) approach to obtain fanout free network implementations with the minimum number of spin diodes. Experimental results have shown that the new proposal obtains better results when compared to the state-of-the-art algorithms that focus on traditional CMOS technology adapted to this new approach.

Exploring the use of approximate TMR to mask transient faults in logic with low area overhead

Abstract The use of Triple Modular Redundancy (TMR) with majority voters can guarantee 100% single fault masking coverage for a given circuit against transient faults. However, this methodology presents a minimum area overhead of 200% compared to the original circuit. In order to reduce considerably the area overhead without compromising significantly the fault coverage, TMR can use approximated logic circuits to generate redundant modules that are optimized for area, compared to the original module. In this work, we propose the use of only approximate logic modules to compose the TMR in order to reduce the area overhead close to minimal values. We use a Boolean factorization based method to compute approximate functions and to select the best composition of approximate logic. The circuits are mapped using the ABC logic synthesis tool and an academic cell library. All the tests are performed using a fault injection tool designed specifically to cope with logic gate and transistor description level. For a combinational circuit (5 inputs, 10 literals) the results have shown that it is possible to maintain the maximum protected p–n junction ratio of 98.88% with only 165% area overhead when using ATMR; and a maximum of 94.66% protected p–n junction ratio with only an 88% area when using full-ATMR. Results for a 4-bit ripple-carry adder showed a protected p–n juncion ratio of almost 97% with 168% area overhead and 93.5% with only 136% area overhead.

Factored Forms for Memristive Material Implication Stateful Logic

This paper proposes the utilization of factored forms in logic synthesis for memristive material implication stateful logic. Factored forms have not been explored by previous works due to expected increasing on device count. We present an algorithm to obtain factored forms computable with minimum number of memristors. Comparison to previous works shows an average reduction of 12% in the number of operations to compute 4-input Boolean functions.