Fikru Adamu-Lema

Integrated atomistic process and device simulation of decananometre MOSFETs

In this paper we present a methodology for the integrated atomistic process and device simulation of decananometre MOSFETs. The atomistic process simulations were carried out using the kinetic Monte Carlo process simulator DADOS, which is now integrated into the Synopsys 3D process and device simulation suite Taurus. The device simulations were performed using the Glasgow 3D statistical atomistic simulator, which incorporates density gradient quantum corrections. The overall methodology is illustrated in the atomistic process and device simulation of a well behaved 35 nm physical gate length MOSFET reported by Toshiba.

Geometry, Temperature, and Body Bias Dependence of Statistical Variability in 20-nm Bulk CMOS Technology: A Comprehensive Simulation Analysis

Conventional bulk CMOS, which is arguably most vulnerable to statistical variability (SV), is the workhorse of the electronic industry for more than three decades. In this paper, the dependence of the SV of key figures of merit on gate geometry, temperature, and body bias in 25-nm gate-length MOSFETs, representative for the 20-nm CMOS technology generation, is systematically investigated using 3-D statistical simulations. The impact of all relevant sources of SV is taken into account. The geometry dependence of the threshold-voltage dispersion (and indeed the dispersion of other key transistor figures of merit) does not necessarily follow the Pelgroms law due to the complex nonuniform channel doping and the interplay of different SV sources. The DIBL variation, for example, follows a log-normal distribution. The temperature significantly affects the magnitudes of threshold voltage, subthreshold slope, ON/OFF currents, and the corresponding statistical distributions. Reverse body bias increases the threshold voltage and its fluctuation, while forward body bias reduces both of them.

Modelling RTN and BTI in nanoscale MOSFETs from device to circuit: A review

In this paper we summarize the impact of Statistical Variability (SV) on device performances and study the impact of oxide trapped charges in combination with SV. Traps time constants are described and analysed in combination with SV and time dependent simulations are performed including SV, random traps and charge injection stochasticity. Finally we demonstrate the necessity of statistical simulations in extracting compact models of aged devices and we address the problem of aged SRAM cell reliability.

3-D Statistical Simulation Comparison of Oxide Reliability of Planar MOSFETs and FinFET

New transistor architectures such as fully depleted silicon on insulator (FDSoI) MOSFETs and FinFETs have been introduced in advanced CMOS technology generations to boost performance and to reduce statistical variability (SV). In this paper, the robustness of these architectures to random telegraph noise and bias temperature instability issues is investigated using comprehensive 3-D numerical simulations, and results are compared with those obtained from conventional bulk MOSFETs. Not only the impact of static trapped charges is investigated, but also the charge trapping dynamics are studied to allow device lifetime and failure rate predictions. Our results show that device-to-device variability is barely increased by progressive oxide charge trapping in bulk devices. On the contrary, oxide degradation determines the SV of SoI and FinFET devices. However, the SoI and multigate transistor architectures are shown to be significantly more robust in terms of immunity to time-dependent SV when compared with the conventional bulk device. The comparative study here presented could be of significant importance for reliability resistant CMOS circuits and systems design.

Interplay between statistical reliability and variability: A comprehensive transistor-to-circuit simulation technology

In this paper we present a reliability simulation framework from atomistic simulations up to circuit simulations, including traps interactions with variability sources. Trapping and detrapping dynamics are reproduced by a kinetic Monte-Carlo engine, which enables oxide degradation simulations such as BTI and RTN phenomenon on large ensembles of atomistic devices. Based on these results compact models are extracted and circuit lifetime projections are derived.

Accuracy and Issues of the Spectroscopic Analysis of RTN Traps in Nanoscale MOSFETs

This paper investigates the limitations to the accuracy and the main issues of the spectroscopic analyses of random telegraph noise (RTN) traps in nanoscale MOSFETs. First, the impact of the major variability sources affecting decananometer MOSFET performance on both the RTN time constants and the trap depth estimation is studied as a function of the gate overdrive. Results reveal that atomistic doping and metal gate granularity broaden the statistical distribution of the RTN time constants far more than what comes from the random position of the RTN trap in the 3-D device electrostatics, contributing, in turn, to a significant reduction of the accuracy of trap spectroscopy. The accuracy is shown to improve the higher is the gate overdrive, owing to a more uniform and gate-bias-independent surface potential in the channel, with, however, the possible drawback of triggering the simultaneous trap interaction with both the channel and the gate. This simultaneous interaction is, finally, shown to critically compromise trap spectroscopy in thin-oxide devices.

Intrinsic parameter fluctuations in conventional MOSFETs until the end of the ITRS: A statistical simulation study

Variability in device characteristics will affect the scaling and integration of next generation nano-CMOS transistors. Intrinsic parameter fluctuations introduced by random discrete dopants, line edge roughness and oxide thickness fluctuations are among the most important sources of variability. In this paper the variability introduced by the above sources is studied in a set of well scaled MOSFETs with channel lengths of 25, 18, 13, and 9 nm. The effect of each source of intrinsic parameter fluctuation is quantified and compared. The random discrete dopants are responsible for the strongest variations followed closely by line edge roughness. The statistical independence of the different sources of fluctuations is also studied in the case of a 35 nm MOSFET.

Problems With the Continuous Doping TCAD Simulations of Decananometer CMOS Transistors

In this paper, we compare results from atomistic and continuous simulation of decananometer scale CMOS transistors. We study the behavior of important figures of merit, including threshold voltage, subthreshold slope, OFF-current, and ON-current. We provide physical explanation for the origin of the discrepancies between the averaged values obtained from the statistical simulations and the results from the continuous doping simulation. Based on our analysis, we clearly demonstrate that there are increasing errors in the doping distributions when device TCAD simulations are calibrated using continuous doping profiles. This questions the use of continuous doping profiles in the routine calibration and TCAD-based optimization of decananometer scale CMOS transistors.

Impact of statistical variability and 3D electrostatics on post-cycling anomalous charge loss in nanoscale Flash memories

This paper presents a detailed simulation investigation of the impact of statistical variability and 3D electrostatics on SILC distribution in nanoscale Flash memories. Considering a 1-TAT model we study the SILC statistics under stationary and dynamic retention conditions. Our results show that SILC is dispersed over the channel area due to non-uniform electrostatics in nanoscale devices. Further, the floating gate poly-silicon granularity plays a major role in determining the SILC distribution, depending on the gate polarity. Dynamic charge loss simulations highlight that the impact of 3D electrostatics is dominant over the cell-to-cell variability. Finally, we analyze the electron emission statistics on a single cell, showing that this gives rise to a lower SILC dispersion than an analytical Poisson charge loss statistics. Our results are fundamental to determine the degree of accuracy of 1D models for the post-cycling charge loss statistics simulation in nanoscale Flash memories.

Statistical Interactions of Multiple Oxide Traps Under BTI Stress of Nanoscale MOSFETs

We report a thorough 3-D simulation study of the correlation between multiple, trapped charges in the gate oxide of nanoscale bulk MOSFETs under bias and temperature instability (BTI). The role of complex electrostatic interactions between the trapped charges in the presence of random dopant fluctuations is evaluated, and their impact on the distribution of the threshold voltage shift and on the distribution of the number of trapped charges is analyzed. The results justify the assumptions of a Poisson distribution of the BTI-induced trapped charges and of the lack of correlation between them, when accounting for time-dependent variability in circuits.