Talib Al-Ameri

Simulation Study of the Impact of Quantum Confinement on the Electrostatically Driven Performance of n-type Nanowire Transistors

In this paper, we have studied the impact of quantum confinement on the performance of n-type silicon nanowire transistors (NWTs) for application in advanced CMOS technologies. The 3-D drift-diffusion simulations based on the density gradient approach that has been calibrated with respect to the solution of the Schrödinger equation in 2-D cross sections along the direction of the transport are presented. The simulated NWTs have cross sections and dimensional characteristics representative of the transistors expected at a 7-nm CMOS technology. Different gate lengths, cross-sectional shapes, spacer thicknesses, and doping steepness were considered. We have studied the impact of the quantum corrections on the gate capacitance, mobile charge in the channel, drain-induced barrier lowering, and subthreshold slope. The mobile charge to gate capacitance ratio, which is an indicator of the intrinsic speed of the NWTs, is also investigated. We have also estimated the optimal gate length for different NWT design conditions.

Nanowire transistor solutions for 5nm and beyond

In this paper we present a comprehensive computational study of silicon nanowire transistor (SNT) and a SNM SRAM cell based on advanced design technology co-optimization (DTCO) TCAD tools. Utilizing this methodology, we provide guidelines and solutions for 5 nm and beyond in CMOS technology. At first, drift-diffusion (DD) results are fully calibrated against a Poisson-Schrodinger (PS) solution to calibrate density-gradient quantum corrections, and ensemble Monte Carlo (EMC) simulations to calibrate transport models. The calibrated DD gives us the capability to simulate statistical variability in nanowire transistors of the 5nm node and beyond accurately and efficiently. Various SNT structures are evaluated in terms of device figures of merit, and optimization of SNTs in terms of electrostatics driven performance is carried out. A variability-aware hierarchical compact model approach for SNT is adopted and used for statistical SRAM simulation near the “scaling limit”. The scaling of SNTs beyond the 5 nm is also discussed.

Correlation between gate length, geometry and electrostatic driven performance in ultra-scaled silicon nanowire transistors

In this work we have investigated the impact of quantum mechanical effects on the device performance of n-type silicon nanowire transistors (NWT) for possible future applications. For the purpose of this paper we have simulated Si NWTs with six different cross-section shapes. However for all devices the cross-sectional area is kept constant in order to provide fair comparison. Additionally we have expanded the computational experiment by including different gate length and gate materials for each of these six Si NWTs. As a result we have established a correlation between the mobile charge distribution in the channel and gate capacitance, drain induced barrier lowering (DIBL) and the sub-threshold slope (SS). The mobile charge to gate capacitance ratio, which is an indicator of the intrinsic speed of the NWTs, is also have been investigated. More importantly all calculations are based on quantum mechanical description of the mobile charge distribution in the channel. This description is based on Schrodinger equation, which is indeed mandatory for nanowires with such ultra-scale dimensions.

Influence of quantum confinement effects and device electrostatic driven performance in ultra-scaled SixGe1−x nanowire transistors

In this work we have investigated the impact of quantum mechanical effects on the device performance of n-type in ultra-scaled SixGe1-x nanowire transistors (NWT) for possible future applications. For the purpose of this paper SixGe1-x NWTs with different SixGe1-x molar fraction has been simulated. However, in all devices the cross-sectional area, dimensions and doping profiles are kept constant in order to provide fair comparison. The design of computational experiment in this work includes nanowire transistors with different gate length of 6nm, 8nm, 10nm, 12nm and 14nm. All wires are simulated with various SixGe1-x ratio. As a result we have established a correlation between the mobile charge distribution in the channel and gate capacitance, drain induced barrier lowering (DIBL) and the sub-threshold slope (SS). The mobile charge to gate capacitance ratio, which is an indicator of the intrinsic speed of the NWTs, is also have been investigated. More importantly all calculations are based on quantum mechanical description of the mobile charge distribution in the channel. This description is based on Schrödinger equation, which is indeed preferred approach for nanowires with such ultra-scale dimensions.

Impact of strain on the performance of Si nanowires transistors at the scaling limit: A 3D Monte Carlo/2D poisson schrodinger simulation study

In this work we investigate the correlation between channel strain and device performance in various n-type Si-NWTs. We establish a correlation between strain, gate length and cross-section dimension of the transistors. For the purpose of this paper we simulate Si NWTs with a <;110> channel orientation, four different ellipsoidal channel cross-sections and five gate lengths: 4nm, 6nm, 8nm, 10nm and 12nm. We have also analyzed the impact of strain on drain-induced barrier lowering (DIBL) and the subthreshold slope (SS). All simulations are based on a quantum mechanical description of the mobile charge distribution in the channel obtained from a 2D solution of the Schrödinger equation in multiple cross sections along the current path, which is mandatory for nanowires with such ultra-scale dimensions. The current transport along the channel is simulated using 3D Monte Carlo (MC) and drift-diffusion (DD) approaches.

Simulation Study of Vertically Stacked Lateral Si Nanowires Transistors for 5-nm CMOS Applications

In this paper, we present a simulation study of vertically stacked lateral nanowires transistors (NWTs), which may have applications at 5-nm CMOS technology. Our simulation approach is based on a collection of simulation techniques to capture the complexity in such ultra-scaled devices. Initially, we used drift-diffusion methodology with activated Poisson–Schrodinger quantum corrections to accurately capture the quantum confinement in the cross-section of the device. Ensemble Monte Carlo simulations are used to accurately evaluate the drive current capturing the complexity of the carrier transport in the NWTs. We compared the current flow in single, double, and triple vertically stacked lateral NWTs with and without contact resistance. The results presented here suggest a consistent link between channel strain and device performance. Furthermore, we propose a device structure for the 5-nm CMOS technology node that meets the required industry scaling projection. We also consider the interplay between various sources of statistical variability and reliability in this paper.

Performance of vertically stacked horizontal Si nanowires transistors: A 3D Monte Carlo/2D Poisson Schrodinger simulation study

In this paper we present a simulation study of 5nm vertically stacked lateral nanowires transistor (NWTs). The study is based on calibration of drift-diffusion results against a Poisson-Schrodinger simulations for density-gradient quantum corrections, and against ensemble Monte Carlo simulations to calibrate carrier transport. As a result of these calibrated results, we have established a link between channel strain and the device performance. Additionally, we have compared the current flow in a single, double and triple vertically stacked lateral NWTs.

Vertically stacked lateral Si80Ge20 nanowires transistors for 5 nm CMOS applications

In this work we present a simulation study of Si80Ge20 and Silicon vertically stacked lateral nanowires transistors (NWTs) with potential application at 5nm CMOS technology node. Our simulation approach is based on careful selection of simulations techniques in order to capture the complexity of such ultra-scaled devices. We have used ensemble Monte Carlo (MC) simulations to accurately predict the drive current considering the complexity of the carrier transport in the NWTs. We have used also drift-diffusion (DD) simulations with quantum corrections based on Poisson-Schrodinger solution to accurately calibrate the density-gradient based DD quantum corrections. Finally, we have benchmarked the current in Si80Ge20 NWTs against Si based NWT.

Invited) Modelling and Simulation of Advanced Semiconductor Devices

This paper presents a modelling and simulation study of advanced semiconductor devices. Different Technology Computer Aided Design approaches and models, used in nowadays research are described here. Our discussions are based on numerous theoretical approaches starting from first principle methods and continuing with discussions based on more well stablished methods such as Drift-Diffusion, Monte Carlo and Non-Equilibrium Green’s Function formalism.