Flynn Carson

Fabrication and packaging of microbump interconnections for 3D TSV

Memory bandwidth has become a bottleneck to processor performance for tera-scale computing needs. To reduce this obstacle, a revolution in package technologies is required for tera-scale computing requirements. 3D TSV (Through Silicon Via) stacking is believed to be one of the technologies that can meet those requirements. In advanced 3D stacking technologies, one of the important steps is to develop and assemble fine pitch, high density solder microbumps. This type of solder microbump in flip chip interconnection provides a high wiring density in silicon die with a high-performance signal and power connection. There is a growing interest in the development and study of this new type of chip stacking and bonding approach for both existing and future devices. This paper will highlight the developments of ultra fine pitch and high density solder microbumps for advanced 3D stacking technologies. A Cu/SnAg solder microbump with 50/40 µm in pitch was fabricated at the silicon wafer level by an electroplating method. The total thickness of the plated Cu and SnAg microbump was 20um. The under bump metallurgy (UBM) layer on the Si carrier used thin film based metal layers. The assembly of the Si chip and the Si carrier was conducted with the thermocompression flip chip bonder at different temperatures, times and pressures and the optimized bonding conditions were obtained. After assembly, the underfill process was carried out to fill the gap and achieve a void free underfilling using a material with a fine filler size. Finally, various reliability tests were carried out for mechanical characterization of microbump interconnections.

3D TSV processes and its assembly/packaging technology

Demand for Through Silicon Via (TSV) is being driven by the need for 3D stacking to shorten interconnection length, increase signal speed, reduce power consumption and reduce power dissipation. Increasing demand for new and more advanced electronic products with a smaller form factor, superior functionality and performance with a lower overall cost has driven the semiconductor industry to develop more innovative and emerging advanced packaging technologies.

Package on Package warpage - impact on surface mount yields and board level reliability

The need to integrate devices in the vertical dimension to reduce space, thickness, and cost for handheld applications has fueled the enormous growth of what can be termed 3D packaging. Due to testability, business flow, and configuration flexibility issues, the package on package (PoP) vertical stacking solution has emerged as the preferred method to stack mobile phone logic processor with memory. The PoP solution typically consists of the logic processor in the bottom package and memory device stack in the top package. The bottom PoP has land pads on the top perimeter in order to allow top PoP to be mounted and reflowed above. Both packages must be capable of being placed on the printed circuit board (PCB) and reflowed simultaneously to each other and to the board. Hence the warpage of the top and bottom PoP relative to each other becomes critical in impacting board mount yields and adoption. This paper presents a systematic study performed to modulate the warpage of the top as well as the bottom PoP and study the effect of the relative warpage of the top and bottom PoP on surface mount (SMT) yields during PoP assembly. A 15times15 mm POP module was selected for this study. This package size represents the higher side of the typical package size spectrum for PoP applications and hence the warpage effects are also magnified. Shadow Moire technique was used for high temperature warpage measurement while subjecting the test samples to a simulated reflow profile. The results of this study can be used as a reference by original equipment manufacturers (OEMs) to define warpage limits to ensure a robust SMT POP stacking yield and board level reliability of the POP module. Further, it can used by integrated device manufacturers (IDMs) and packaging subcontractors to determine the kind of material set and construction required to meet specific warpage targets and be compatible with the other package in the PoP stack. This represents a significant advancement over the current practice of procuring the top and bottom packages manufactured independent of each other and reactively dealing with SMT yield issues.

Controlling Top Package Warpage for POP Applications

The need to integrate devices in the vertical dimension to reduce space, thickness, and cost for handheld applications has fueled enormous growth of what can be termed 3D packaging. Due to testability, business flow, and configuration flexibility issues, the package on package (POP) vertical stacking solution has emerged as the preferred method to stack mobile phone logic processor with memory. The POP solution typically consists of the logic processor in the bottom package and memory device stack in the top package. The bottom package has land pads on the top perimeter in order to allow top package to be mounted and reflowed above. Both packages must be capable of being placed on the PC board and reflowed simultaneously to each other and to the board. Control of the top and bottom package warpage is a critical issue impacting board mount yields and adoption. A series of experiments were performed to determine the impact of different materials and construction on the warpage of the top package at reflow temperature. From this work certain trends are apparent and can be used to optimize the top package warpage to assure compatibility of warpage with the bottom POP and high yields during the simultaneous reflow of the POP stack to the motherboard.

Development of Super Thin TSV PoP

One of the hottest topics in the semiconductor industry today is a 3D packaging using Through Silicon Via (TSV) technology. Driven by the need for improved electrical performance or the reduction of timing delays, methods to use short vertical interconnects have been developed to replace the long interconnects found in 2D packaging. 3D TSV interposer is an efficient and practical approach to solving die integration challenges. Many microsystem devices that will have to move to wafer-level packages will also facilitate further integration using silicon TSV interposers. This paper will address TSV interposer development for mobile applications to replace normal organic laminate substrate. Major driver of this work is for PoP thickness reduction since current organic PoP is one of the thickest components in cellular phone engine. Super Thin PoP test vehicle was designed in order to prove the viability of this technology. This test vehicle was a 12×12mm package with 0.4mm ball pitch on the bottom and 0.4mm pitch between the top and bottom PoP package. Test vehicle has 0.1mm thick TSV substrate and bare-die flip-chip, achieving 0.7mm total stackup height vs. equivalent organic PoP of ∼1.5mm. This paper will highlight the TSV interposer test vehicle design, fabrication, assembly process development, warpage behavior study with simulation and experimentals, component level reliability test results of the Super Thin PoP test vehicle and future steps.

The development of the Fan-in Package-on-Package

Package-on-package (PoP) has become the preferred means of stacking logic processors and memory for advanced mobile phones. The challenge is to reduce size, thickness, and cost of this PoP solution. The fan-in package-on-package (FiPoP) has been developed to address such concerns as well as enable more device integration while maintaining the desirable PoP business model. This paper will detail the development of the FiPoP to meet the size, thickness, flatness, and package level and board level reliability requirements of the typical handset application.

Die to die copper wire bonding enabling low cost 3D packaging

Copper wire replacing gold wire in IC packaging has emerged as a major trend in the packaging industry. The steady and sustained increase in gold (Au) prices in recent years combined with the constant need to reduce the cost of IC packaging is driving this replacement of Au wires with copper (Cu) wires. The maturation of Cu wire is resulting in widespread adoption across many device application and package types. This adoption of Cu wire appears to have invigorated the industry and held off the long predicted demise of wire bonding [1]. The cost benefits associated with converting to Cu wire are being sought for more advanced packaging solutions such as 3D packaging and System in Package (SiP). Such package solutions typically require die to die wire bonding and/or reverse wire bonding, which is closely related. Thus, providing die to die Cu wire bonding capability is an essential step towards enabling the copper wire transition for advanced package types. This paper will highlight the development of die to die wire bonding with Cu wire and will show the results of reliability tests demonstrating the capability of the developed die to die Cu wire bonding package solution.

Thermal and electrical characterization of eWLB (embedded Wafer Level BGA)

Demand for Wafer Level Package (WLP) is being driven by the need to shrink package size and height, simplify the supply chain and provide a lower overall cost by using the infrastructure of a batch process. WLP is the upcoming future packaging technology. The driving factors for the implementation of this packaging technology are the low packaging and test cost, the excellent electrical and thermal performance, the ability to work with increasing interconnect density on chip side and the potential for integration of functionality. The increasing demand for new and more advanced electronic products with smaller form factor and superior functionality and performance, is driving the integration of functionality into the third dimension. There are some restrictions in possible applications for Fan-in (FI) WLPs since global chip trends tend toward smaller chip areas with an increasing number of interconnects. The shrinkage of the pitches and pads at the chip to package interface is happening much faster than the shrinkage at the package to board interface. This interconnection gap requires Fan-out (FO) packaging, where the package size is larger than the chip size in order to provide a sufficient area to accommodate the second level interconnect. eWLB is a type of FO-WLP that has the potential to realize any number of interconnects with standard pitches at any shrink stage of the wafer node technology. This paper will highlight some of the recent characterization works of thermal and electrical performance of eWLB package. The performance compared with other packaging format, i.e. FI-WLP and other array packages is discussed with simulation data. Based on computational fluidic dynamics (CFD) simulation, Θja of eWLB package is calculated and it was comparable with FI-WLPs. Thermal characterization activity is carried out to investigate the effect on eWLB configuration with power loading. Thin film based passives on the FO area (mold material) of the eWLB is also analyzed during electrical characterization. Due to the low-loss property of the mold material, plated Cu inductors showed high quality-factor (Q) performance. The mold material in FO area is not only used as a supporting substrate, but also serves as the package substrate, which allows the high-Q inductors to be implemented with other RF chips in one single package. In addition, parasitic (RLC) electrical performance results will be presented in this paper too.

Three-tier PoP configuration utilizing flip chip Fan-in PoP bottom package

The increasing demand for functionality and performance in mobile handsets has driven the requirement for separate modem and application processors with requisite memory. PoP has helped reduce the footprint of each processor and memory package combination on the PCB. Stacking the processors and memory in a single three-tier PoP configuration would further reduce the footprint. This paper details the development of such a three-tier PoP configuration, utilizing Fan-in PoP technology for the bottom PoP. The developed three-tier PoP test vehicle successfully exhibited good surface mount yield and excellent board level drop test and temperature cycle performance.

Study of Pd mixing during Pd-Cu wire ball formation and impact on wire bond quality

The skyrocketing price of gold has driven the rapid adoption of copper wire in semiconductor packaging. Cu wire is being used for increasingly advanced applications requiring copper wire bond to finer bond pad geometries and structures. Palladium coated Cu wire (Pd-Cu wire) has emerged as the preferred material to realize the cost benefits of Cu wire while achieving the same yield and reliability levels as Au wire. However, during the ball bond formation, the Pd-Cu wire is melted causing mixing of the Pd and Cu. This paper presents the results of a fundamental study of Pd-Cu wire mixing during the ball formation process. An Electronic Flame Off (EFO) process is used to form the ball. Pd mixing in the ball due to the EFO condition is studied. Visual appearance and quality of the ball will also be evaluated. Several bonding wires suppliers are analyzed. Resultant hardness of formed ball is measured. The impact on the stability of the bonding process to the aluminum bond pad is studied, including analysis of the bond interface and Al splash during bonding. Through this study fundamental insight into the variability of Pd mixing and appearance in formed ball related to wire supplier and EFO parameter is gained.