In Sang Yoon

3-D Stacked Package Technology and Trends

The need to integrate more device technology in a given board space for handheld applications such as mobile phones has driven the adoption of innovative packages which stack such devices in the vertical or third dimension (3D). Stacking of device chips in small and thin fine-pitch ball grid array packages has evolved into the stacking of packages themselves to achieve the same end. The advantage of stacking packages rather than device chips is that packages can be fully tested good prior to stacking. There are two primary ways to stack packages to achieve such vertical integration: package-on-package (PoP) and package-in-package (PiP). Innovative variations of PoP and PiP are being developed to address specific packaging needs and market trends. This paper will detail some of the key technology supporting PoP and PiP packages currently in production and the development of new variations of such packages to address future trends.

The development of the Fan-in Package-on-Package

Package-on-package (PoP) has become the preferred means of stacking logic processors and memory for advanced mobile phones. The challenge is to reduce size, thickness, and cost of this PoP solution. The fan-in package-on-package (FiPoP) has been developed to address such concerns as well as enable more device integration while maintaining the desirable PoP business model. This paper will detail the development of the FiPoP to meet the size, thickness, flatness, and package level and board level reliability requirements of the typical handset application.