Francesco Gatta

A 0.18/spl mu/m CMOS direct-conversion receiver front-end for UMTS

The authors present a direct-conversion receiver front-end IC which contains LNA, quadrature mixers and VGAs, realized in 0.18 μm CMOS technology. It has +48.8 dBm IIP2, -6 dBm in band IIP3 (-2 dBm out of band 113), 6.2 dB DSB NF integrated in a 10 kHz-1.92 MHz band and draws 15 mA from a 1.8 V supply.

A 2 dB NF, fully differential, variable gain, 900 MHz CMOS LNA

A fully differential 900 MHz CMOS LNA using, as input stage, nMOS and pMOS inductively degenerated pairs, in shunt configuration, achieves the following performance: 2 dB NF, 22 dB voltage gain, -3 dBm IIP3 with 8 mA current consumption. As additional feature of this LNA is a variable gain. Measurements have been performed on packaged dies. No external components are used, except for an SMD inductor (used for tuning purposes), placed in series with the on-chip gate spiral inductor.

An Embedded 65 nm CMOS Baseband IQ 48 MHz–1 GHz Dual Tuner for DOCSIS 3.0

An embedded CMOS digital dual tuner for DOCSIS 3.0 and set-top box applications is presented. The dual tuner down-converts a total of ten 6 MHz Annex B channels or eight 8 MHz Annex A channels, for a maximum data rate of 320 Mb/s in Annex B and 400 Mb/s in Annex A mode. The dual tuner exceeds all the stringent SCTE 40 specifications over the 48-1004 MHz bandwidth, without using any external components or SAW filters. Enabling technologies are a harmonic rejection front-end, a low-noise high-frequency resolution PLL, and digital image rejection. To our knowledge this is the first reported multichannel broadband tuner embedded in a DOCSIS 3.0 System on a chip implemented in 65 nm pure digital CMOS technology.

An embedded 65 nm CMOS baseband IQ 48 MHz-1 GHz dual tuner for DOCSIS 3.0

An embedded CMOS digital dual tuner for DOCSIS 3.0 and set-top box applications is presented. The dual tuner down-converts a total of ten 6 MHz Annex B channels or eight 8 MHz Annex A channels, for a maximum data rate of 320 Mb/s in Annex B and 400 Mb/s in Annex A mode. The dual tuner exceeds all the stringent SCTE 40 specifications over the 48-1004 MHz bandwidth, without using any external components or SAW filters. Enabling technologies are a harmonic rejection front-end, a low-noise high-frequency resolution phase-locked loop (PLL) and digital image rejection. To our knowledge this is the first reported multi-channel Broadband Tuner embedded in a DOCSIS 3.0 System on a Chip implemented in a 65 nm pure digital CMOS technology.

An embedded 65nm CMOS low-IF 48MHz-to-1GHz dual tuner for DOCSIS 3.0

The increased competition to deliver broadband data to the home (including GPON and VDSL) is motivating cable providers to deliver data rates which far exceed what is presently available based on the DOCSIS 1.x and DOCSIS 2.0 standards. The DOCSIS 3.0 standard provides this bandwidth increase as well as additional flexibility, where higher data throughput can be obtained by bonding together multiple downstream (DS) channels. This standard calls for the ability to bond any 4 channels in a 64MHz contiguous RF bandwidth. Solutions that allow even more channel bonding and provide more flexibility in the allocated frequency spectrum are preferred. This paper reports an embedded dual-tuner architecture able to select two independent 32MHz frequency bands, allowing for a maximum of 10 demodulated 6MHz Annex B DS channels. In Fig. 6.6.1 the top level block diagram is shown: an external LNA amplifies the RF signal which drives an internal splitter, followed by the two low-IF tuners. Each tuner downconverts 5 DS channels to IF frequencies centered at 0MHz (CH 0), +6MHz (CH +1), +12MHz (CH +2), −6MHz (CH −1) and −12MHz (CH −2). Channels +1 and +2 lie at the images of channels −1 and −2 respectively. Any or all channels can be selected for demodulation by the SoC, up to a maximum of eight. Image rejection is enhanced digitally, taking advantage of the tuner integration into the SoC.