Pierre Malinge

A one transistor cell on bulk substrate (1T-Bulk) for low-cost and high density eDRAM

A 1T cell for high-density eDRAM has been successfully developed on bulk silicon substrate for the first time. The device architecture is fully compatible with CMOS logic process integration, allowing very low chip cost for SoC applications. Experimental results show a retention time over 1s at 25/spl deg/C and 100ms at 85/spl deg/C, which is compatible with eDRAM requirements. Non-destructive readout is experimentally demonstrated at 85/spl deg/C. The integration of the memory cell in a matrix arrangement is evaluated. Gate and drain disturb are characterized, showing enough disturb margins for memory operations.

Further insight into the physics and modeling of floating-body capacitorless DRAMs

In this paper, we report on parasitic bipolar conduction occurring in floating-body effect based capacitor-less DRAMs. A way to include these effects into a previously developed model is presented. The enhanced model is then compared with electrical data realized on triple-well nMOSFET devices within the 26/spl deg/C-100/spl deg/C temperature range.

An 8 Mbit DRAM design using a 1 Tbulk cell

An 8 Mbit memory chip featuring a floating body one transistor cell on bulk substrate is characterized for the first time. A high-speed and high accuracy current sense-amplifier with a large common mode reference current is proposed. It achieves a reading time of 10 ns and a current read margin lower than 5 /spl mu/A. A bit fail rate of 0.017% was measured on a 1 Mbit module. Data retention shows that 1 Tbulk cell concept has the potential to be used as a future eDRAM memory cell.

Scaled IT-Bulk devices built with CMOS 90nm technology for low-cost eDRAM applications

A one transistor DRAM cell realized on bulk substrate (lT-Bulk) with CMOS 90nm platform is presented for the first time. The device fabrication is fully compatible with logic process integration and includes only few additional steps, thus making this IT cell very attractive for low-cost embedded memories. Very scaled devices were fabricated with a gate length down to 80nm and several gate oxide thicknesses: their performances in terms of memory effect amplitude, retention time and disturb margins are very promising for future high density eDRAM.

High performance bulk planar 20nm CMOS technology for low power mobile applications

In this paper, we present a high performance planar 20nm CMOS bulk technology for low power mobile (LPM) computing applications featuring an advanced high-k metal gate (HKMG) process, strain engineering, 64nm metal pitch & ULK dielectrics. Compared with 28nm low power technology, it offers 0.55X density scaling and enables significant frequency improvement at lower standby power. Device drive current up to 2X 28nm at equivalent leakage is achieved through co-optimization of HKMG process and strain engineering. A fully functional, high-density (0.081um2 bit-cell) SRAM is reported with a corresponding Static Noise Margin (SNM) of 160mV at 0.9V. An advanced patterning and metallization scheme based on ULK dielectrics enables high density wiring with competitive R-C.

A 750 K Photocharge Linear Full Well in a 3.2 μm HDR Pixel with Complementary Carrier Collection

Mainly driven by automotive applications, there is an increasing interest in image sensors combining a high dynamic range (HDR) and immunity to the flicker issue. The native HDR pixel concept based on a parallel electron and hole collection for, respectively, a low signal level and a high signal level is particularly well-suited for this performance challenge. The theoretical performance of this pixel is modeled and compared to alternative HDR pixel architectures. This concept is proven with the fabrication of a 3.2 μm pixel in a back-side illuminated (BSI) process including capacitive deep trench isolation (CDTI). The electron-based image uses a standard 4T architecture with a pinned diode and provides state-of-the-art low-light performance, which is not altered by the pixel modifications introduced for the hole collection. The hole-based image reaches 750 kh+ linear storage capability thanks to a 73 fF CDTI capacitor. Both images are taken from the same integration window, so the HDR reconstruction is not only immune to the flicker issue but also to motion artifacts.