Rossella Ranica

A one transistor cell on bulk substrate (1T-Bulk) for low-cost and high density eDRAM

A 1T cell for high-density eDRAM has been successfully developed on bulk silicon substrate for the first time. The device architecture is fully compatible with CMOS logic process integration, allowing very low chip cost for SoC applications. Experimental results show a retention time over 1s at 25/spl deg/C and 100ms at 85/spl deg/C, which is compatible with eDRAM requirements. Non-destructive readout is experimentally demonstrated at 85/spl deg/C. The integration of the memory cell in a matrix arrangement is evaluated. Gate and drain disturb are characterized, showing enough disturb margins for memory operations.

A capacitor-less DRAM cell on 75nm gate length, 16nm thin fully depleted SOI device for high density embedded memories

A capacitor-less DRAM cell on very thin film (Tsi=16nm) and short gate length (Lg=75nm) fully depleted (FD) device is demonstrated for the first time. Memory operations mechanisms are presented and retention time compatible to eDRAM requirements is measured at 85/spl deg/C. Nondestructive reading is demonstrated at 25/spl deg/C and disturb margins are deeply investigated, showing the possibility of matrix integration. This study is then extended to another type of FD device: the very promising double gate architecture.

An 8 Mbit DRAM design using a 1 Tbulk cell

An 8 Mbit memory chip featuring a floating body one transistor cell on bulk substrate is characterized for the first time. A high-speed and high accuracy current sense-amplifier with a large common mode reference current is proposed. It achieves a reading time of 10 ns and a current read margin lower than 5 /spl mu/A. A bit fail rate of 0.017% was measured on a 1 Mbit module. Data retention shows that 1 Tbulk cell concept has the potential to be used as a future eDRAM memory cell.

Quantum effects influence on thin silicon film capacitor-less DRAM performance

As DRAM integration follows CMOS interest for thin silicon films, we analyze the impact of quantum effects on capacitor-less DRAM based on floating-body effect. Quantum effects significantly reduce the memory effect when silicon film reaches 10nm but their major impact is for thin and undoped silicon film

Scaled IT-Bulk devices built with CMOS 90nm technology for low-cost eDRAM applications

A one transistor DRAM cell realized on bulk substrate (lT-Bulk) with CMOS 90nm platform is presented for the first time. The device fabrication is fully compatible with logic process integration and includes only few additional steps, thus making this IT cell very attractive for low-cost embedded memories. Very scaled devices were fabricated with a gate length down to 80nm and several gate oxide thicknesses: their performances in terms of memory effect amplitude, retention time and disturb margins are very promising for future high density eDRAM.

A Cost-Effective Low Power Platform for the 45-nm Technology Node

This paper presents a cost-effective 45-nm technology platform, primarily designed to serve the wireless multimedia and consumer electronics needs. This platform features low power transistors operating at a nominal voltage of 1.1V, an ultra low k dielectric (k~2.5) with up to 9 Cu metal layers and 0.25/0.3/0.37mum2 SRAM cells. This platform also features an optional third gate oxide for either higher speed or active power mitigation. This technology has been developed on the (100)-oriented substrate with a key focus on process simplicity. Transistor improvement relies on mask-free strain engineering techniques along with co-implanted halos and laser anneal. The impact of laser anneal on transistor reliability and mixed-signal capabilities are also examined. Drive current as high as 660/320 muA/mum at 1nA/mum and 1.1V are reported

A new 40-nm SONOS structure based on backside trapping for nanoscale memories

Silicon-on-nothing (SON) devices have been analyzed for the first time in view of nanoscaled nonvolatile memories (NVM) applications. Two reliable steady states have been demonstrated using backside charge trapping in the nitride layer under the channel as a memory effect in a 40-nm gate-length pMOS silicon-oxide-nitride-oxide-silicon device realized with SON technology. Low voltages (/spl sim/3 V) are required for memory operations and a threshold voltage memory window superior to 0.5 V can be achieved. Charge loss mechanism is analyzed and very promising data retention behavior is demonstrated at 125/spl deg/C. This architecture, with a storage node localized under the channel, is exactly the same device that can operate as a high-performance transistor at low voltages and as an NVM cell at higher voltage ranges. A total compatibility between logic and the embedded NVM process is thus insured. In view of high-density memories, the feasibility of 2-bit storage in a longer SON device is also demonstrated.

28nm FDSOI technology sub-0.6V SRAM Vmin assessment for ultra low voltage applications

Vmin measurements in 28nm FDSOI technology on 128Mb SRAM bitcells from -40°C to 125°C are reported in this paper. Adding the silicon ageing behavior and the process variability, we have developed a complete model and demonstrated end-of-life SRAM Vmin of 0.6V and 0.5V on 20Mb with 0.120μm2 and 0.152μm2 bitcells, respectively. This is the first report of a such extensive SRAM Vmin assessment at the 28nm node. The construction of write limited bitcells, combined with write assist design technique, was found to be the most efficient way to achieve ultra low Vmin in 28nm FDSOI technology. In addition, Vmin retention below 0.4V is demonstrated in 0.120μm2 bitcells, leading to the enablement of ultra-low leakage bitcells with 2pA/cell in retention mode.

Modeling the Independent Double Gate Transistor in Accumulation Regime for 1TDRAM Application

This paper details the modeling of a one-transistor dynamic random-access memory (1TDRAM) based on an independent double-gate device. A pseudo-2-D compact model of memory operations and dynamic behavior of data retention is proposed. The physical mechanisms involved are calculated through the accumulated charge in the body modulated by quantum effects related to thin silicon films. The resulting currents from programming operations are detailed. We consider current leakages, generation/recombination, and band-to-band tunneling parasitic effects for data retention.

Understanding the Effect of Laser Anneal on LSTP 45nm Node MOS Transistor Electrical Parameters

The 45nm technological node MOS transistor has been optimized thanks to DSA (dynamic surface annealing) technique, and an indepth analysis of the MOS transistors electrical parameters is provided for the first time. This anneal, immediately following the main dopants activation spike anneal, is shown to improve both Cox and access resistance thanks to the dopants over-activation. However, at too high laser power, it reduces the carriers mobility and the hot carriers related lifetime because of interface states generation. Thus, a compromise has to be found for the saturation current optimization. Introduction In order to meet the 45nm node requirements, making thin and unresistive junctions is one of the key challenges, at least with bulk silicon technologies where the junction thickness is determined by the dopants implant and diffusion. The control of the junction thickness directly impacts the short channel effects, while the source and drain activation impacts the saturation current, via the access resistance. Using a laser anneal immediately after the main dopants activation spike anneal was shown to increase the dopant activation by enhancing the solubility limit, without any diffusion process [1-4]. Furthermore, over-activating the gate dopants also allows increasing the oxide capacitance by reducing the polydepletion. However, the impact of the laser anneal on the second order parameters such as device mobility, access resistance and interface quality still has to be quantified and understood in order to allow the optimization of the laser conditions. Experimental conditions: process parameters The following experiments were led on our 45nm node technology platform [5] on the LSTP (low stand-by power) device, featuring traditional SiON gate dielectric with polysilicon gate, <100> rotated substrate for the PMOS mobility optimization, and CESL (contact etch stop layer) stress / SMT (stress memory technique) combination for the NMOS optimization via tensile stress [6]. By changing the laser power, various silicon surface anneal temperatures where explored, between 1030°C and 1320°C, plus a no laser anneal reference (17 wafers tested). Experimental conditions: measurement methodology The effect of the laser anneal on lateral junctions diffusion could be measured directly on the transistors thanks to a capacitance-based methodology [7] allowing a precise (<1nm) direct measurement of the effective channel length. Our method is based on the proportionality of the gate-to-channel capacitance to the electric length, with adequate parasitic capacitances measurement (fig. 1). The poly length was measured in the same way on transistors without SDE (Source and Drain Extensions) and pocket implants, and therefore the total overlap length could be computed. The low field mobility was computed using the transconductance gain (β) of the transistor measured with the Hamer method [8]. Whereas it only monitors the mobility at low field, as an extrapolation at zero inversion charge, it is actually representative of our LSTP technology where the working point is at relatively low transverse field, due to a low Vdd and a high threshold voltage. Furthermore, it is applicable to the short gate length transistors, providing the electric gate length is known, thanks to an intrinsic substraction of the parasitic resistances effect. The effective mobility was also measured on the long transistors by the conventional split CV method [9]. The access resistances were computed from the Hamer method parameters θ and β [10]. This method allows the determination of the series resistance without any assumption neither on the mobility nor on the gate length. Qualitative indications on the interface states density have been obtained from the maximum charge pumping current, even if, due to thin oxide related gate leakage, effective traps density computation is problematic. Finally, the saturation current at a constant gate voltage overdrive (Vg-Vth) was measured, in order to get a global performance indicator while getting rid of the threshold voltage variations. Impact of the laser on the electrical parameters First, the laser annealing is shown to have very limited effect on the lateral dopants diffusion. Indeed, on the N channel transistor, the maximum overlap length variation is around 1nm, close to the technique precision and the process dispersion (fig. 2). If we examine the effect of the laser annealing on the Ion performance measured at constant gate voltage overdrive, we show completely different behaviours of the NMOS and PMOS. NMOS saturation current is improved by 6% in the no laser to 1200°C laser anneal range, then slightly degraded at higher temperature (fig. 3). In the meanwhile, the PMOS transistor exhibits very low effect under 1200°C, but significant improvement at high laser temperature. However, the HCI (hot carriers injection) related degradation increases when the temperature is increased above 1200°C (fig. 4) ; thus, a compromise has to be found between, NMOS and PMOS performance and reliability. This different behaviour between NMOS and PMOS can be explained by the measurement of the Cox and access resistance. Indeed, whereas the PMOS Cox increases continuously over all the temperature range (fig. 5), the NMOS Cox saturates over 1200°C, explaining the Ion current optimum. The strong improvement of the PMOS access resistance (fig. 6) at high temperature also explains the Ion improvement in this range, whereas the NMOS access resistance improvement is spread over the temperature range (fig.7). However, the improvement of the Cox and Rsd should theoretically induce a stronger Ion increase, especially for the PMOS in the low temperature range. But if we examine the low field mobility (μ0) as a function of the laser temperature (fig. 8), we notice degradation at high laser temperature, in particular above 1200°C. This transport degradation can also be shown on long channel transistors (L=10μm) thanks to split-CV measurements (fig. 9), but cannot be explained by a channel dopants activation. Indeed, if we compute the channel doping by integrating the measured depletion charge, no effective doping difference can be detected (fig. 10). Considering also that the mobility degradation is more pronounced at low transverse field than at high field (but still very effective on the performance, due to a low field working point), it seems to be linked to Coulomb scattering, and possibly to interface traps density. This can be evidenced by the charge pumping current, increased when increasing the laser temperature, both on the nominal and high gate length transistor (fig. 11), explaining both the mobility and the HCI lifetime evolution, as HCI degradation is induced by interface states generation. Conclusion The NMOS and PMOS transistors saturation currents can be improved by the additional laser anneal, thanks to Cox and Rsd improvement. However, for the PMOS transistor, the improvement is mainly seen over 1200°C anneal temperature; in this temperature range, the mobility and HCI lifetime are degraded, for NMOS and PMOS, due to interface states generation. Thus, a trade-off has to be found between NMOS and PMOS performance optimization and lifetime. These results will have to be taken into account for multiple laser anneal processes under study for the next technological node [11-12]. Extended Abstracts of the 2008 International Conference on Solid State Devices and Materials, Tsukuba, 2008, -870B-8-2 pp. 870-871