Alexandre Villaret

A one transistor cell on bulk substrate (1T-Bulk) for low-cost and high density eDRAM

A 1T cell for high-density eDRAM has been successfully developed on bulk silicon substrate for the first time. The device architecture is fully compatible with CMOS logic process integration, allowing very low chip cost for SoC applications. Experimental results show a retention time over 1s at 25/spl deg/C and 100ms at 85/spl deg/C, which is compatible with eDRAM requirements. Non-destructive readout is experimentally demonstrated at 85/spl deg/C. The integration of the memory cell in a matrix arrangement is evaluated. Gate and drain disturb are characterized, showing enough disturb margins for memory operations.

A capacitor-less DRAM cell on 75nm gate length, 16nm thin fully depleted SOI device for high density embedded memories

A capacitor-less DRAM cell on very thin film (Tsi=16nm) and short gate length (Lg=75nm) fully depleted (FD) device is demonstrated for the first time. Memory operations mechanisms are presented and retention time compatible to eDRAM requirements is measured at 85/spl deg/C. Nondestructive reading is demonstrated at 25/spl deg/C and disturb margins are deeply investigated, showing the possibility of matrix integration. This study is then extended to another type of FD device: the very promising double gate architecture.

Further insight into the physics and modeling of floating-body capacitorless DRAMs

In this paper, we report on parasitic bipolar conduction occurring in floating-body effect based capacitor-less DRAMs. A way to include these effects into a previously developed model is presented. The enhanced model is then compared with electrical data realized on triple-well nMOSFET devices within the 26/spl deg/C-100/spl deg/C temperature range.

An 8 Mbit DRAM design using a 1 Tbulk cell

An 8 Mbit memory chip featuring a floating body one transistor cell on bulk substrate is characterized for the first time. A high-speed and high accuracy current sense-amplifier with a large common mode reference current is proposed. It achieves a reading time of 10 ns and a current read margin lower than 5 /spl mu/A. A bit fail rate of 0.017% was measured on a 1 Mbit module. Data retention shows that 1 Tbulk cell concept has the potential to be used as a future eDRAM memory cell.

Quantum effects influence on thin silicon film capacitor-less DRAM performance

As DRAM integration follows CMOS interest for thin silicon films, we analyze the impact of quantum effects on capacitor-less DRAM based on floating-body effect. Quantum effects significantly reduce the memory effect when silicon film reaches 10nm but their major impact is for thin and undoped silicon film

Scaled IT-Bulk devices built with CMOS 90nm technology for low-cost eDRAM applications

A one transistor DRAM cell realized on bulk substrate (lT-Bulk) with CMOS 90nm platform is presented for the first time. The device fabrication is fully compatible with logic process integration and includes only few additional steps, thus making this IT cell very attractive for low-cost embedded memories. Very scaled devices were fabricated with a gate length down to 80nm and several gate oxide thicknesses: their performances in terms of memory effect amplitude, retention time and disturb margins are very promising for future high density eDRAM.

A new 40-nm SONOS structure based on backside trapping for nanoscale memories

Silicon-on-nothing (SON) devices have been analyzed for the first time in view of nanoscaled nonvolatile memories (NVM) applications. Two reliable steady states have been demonstrated using backside charge trapping in the nitride layer under the channel as a memory effect in a 40-nm gate-length pMOS silicon-oxide-nitride-oxide-silicon device realized with SON technology. Low voltages (/spl sim/3 V) are required for memory operations and a threshold voltage memory window superior to 0.5 V can be achieved. Charge loss mechanism is analyzed and very promising data retention behavior is demonstrated at 125/spl deg/C. This architecture, with a storage node localized under the channel, is exactly the same device that can operate as a high-performance transistor at low voltages and as an NVM cell at higher voltage ranges. A total compatibility between logic and the embedded NVM process is thus insured. In view of high-density memories, the feasibility of 2-bit storage in a longer SON device is also demonstrated.

Fabrication and Room-Temperature Single-Charging Behavior of Self-Aligned Single-Dot Memory Devices

Self-aligned single-dot memory devices and arrays were fabricated based on arsenic-assisted etching and oxidation effects. The resulting device has a floating gate of about 5-10 nm, presenting single-electron memory operation at room temperature. In order to realize the final single-electron memory circuit, this paper investigates process repeatability, device uniformity in single-dot memory arrays, device scalability, and process transferability to an industrial application

Inverse Lithography Technique for advanced CMOS nodes

Resolution Enhancement Techniques have continuously improved over the last decade, driven by the ever growing constraints of lithography process. Despite the large number of RET applied, some hotspot configurations remain challenging for advanced nodes due to aggressive design rules. Inverse Lithography Technique (ILT) is evaluated here as a substitute to the dense OPC baseline. Indeed ILT has been known for several years for its near-to-ideal mask quality, while also being potentially more time consuming in terms of OPC run and mask processing. We chose to evaluate Mentor Graphics’ ILT engine “pxOPCTM” on both lines and via hotspot configurations. These hotspots were extracted from real 28nm test cases where the dense OPC solution is not satisfactory. For both layer types, the reference OPC consists of a dense OPC engine coupled to rule-based and/or model-based assist generation method. The same CM1 model is used for the reference and the ILT OPC. ILT quality improvement is presented through Optical Rule Check (ORC) results with various adequate detectors. Several mask manufacturing rule constraints (MRC) are considered for the ILT solution and their impact on process ability is checked after mask processing. A hybrid OPC approach allowing localized ILT usage is presented in order to optimize both quality and runtime. A real mask is prepared and fabricated with this method. Finally, results analyzed on silicon are presented to compare localized ILT to reference dense OPC.

Study of SRAF placement for contact at 45 nm and 32 nm node

At 45 and 32 nm nodes, one of the most critical layers is the Contact one. Due to the use of hyper NA imaging, the depth of focus starts to be very limited. Moreover the OPC is rapidly limited because of the increase of the pattern density. The limited surface in the dark field region of a Contact layer mask enforces the edges movement to stop very quickly. The use of SRAF (Sub Resolution Assist Feature) has been widely use for DOF enhancement of line and space layers since many technology node. Recently, SRAF generated using inverse lithography have shown interesting DOF improvement1. However, the advantage of the ideal mask generated by inverse lithography is lost when switching to a manufacturable mask with Manhattan structures. For SRAF placed in rule based as well as Manhattan SRAF generated after inverse lithography, it is important to know what their behavior is, in term of size and placement. In this article we propose to study the placement of scatter-trenches assist features for the contact layer. For this we have performed process window simulation with different SRAF sizes and distance to the main OPC. These results permit us to establish the trends for size and placement of the SRAF. Moreover we have also take a look of the advantages of using 8 surrounding SRAF (4 in vertical - horizontal and 4 at 45°) versus 4 surrounding SRAF. Based on these studies we have seen that there is no real gain of increasing the complexity by adding additional SRAF.