Jeffrey T. Coffin

Effects of parylene coating on the thermal fatigue life of solder joints in ceramic packages

A study was undertaken to determine the effectiveness of a thin layer (9.4 mu m in thickness) of a chemical vapor deposited polymer, parylene, in enhancing the solder lifetime of a ceramic package containing large-DNP (distance to neutral point) test chips. Both coated and uncoated (control) packages with chips joined via C4 Pb/Sn solder technology were thermally cycled near room temperature and liquid nitrogen temperature (-196 degrees C) until solder failure was first noticed in coated packages. The number of cycles to first failure for coated packages was found to be twice the corresponding number for uncoated packages. To interpret this twofold solder life enhancement, an elasto-plastic finite-element model was developed. Based on the results provided by this model and a low-temperature solder lifetime model, it was possible to attribute the extended solder life to the modification of the strain and stress fields in the solder joints by the parylene coating. The model also suggests that the solder life can be prolonged significantly with a parylene coating as thin as 3 mu m. >

Parylene encapsulation of ceramic packages for liquid nitrogen application

A study was undertaken to determine the effectiveness of a thin layer (9.4 mu m in thickness) of a chemical-vapor-deposited polymer, Parylene, in enhancing the solder lifetime of IBM ceramic packages containing large-DNP (distance to neutral point) test chips during liquid-nitrogen operation. Coated and uncoated (control) packages with chips joined using C4 (controlled collapse chip connection) Pb/Sn solder technology were thermally cycled between near room temperature and liquid-nitrogen temperature. At every 50 or 100 cycles, the electrical resistances of solder joints were measured at room temperature for the nondestructive detection of solder failures based on a solder electrical-resistance criterion. The thermal cycling experiment and electrical measurement were continued until solder failure was first noticed in coated packages. The number of cycles to first failure was twice the corresponding number for uncoated packages. To help interpret this two-fold solder-life enhancement associated with parylene, an elastoplastic finite-element model was developed and used to determine the thermal strain and stress distributions near failed solder joints for coated and uncoated packages during thermal cycling. Based on the results provided by this model and a low-temperature solder lifetime model, the extended solder life was attributed to the ability of Parylene to modify the strain and stress fields in the solder joint as well as to its barrier and conformal-coating properties.<<ETX>>

Delamination mechanisms of thermal interface materials in organic packages during reflow and moisture soaking

A thermal interface material (TIM) is typically a compliant material with high thermal conductivity that is applied between a heat-generating chip and a heat spreader in an electronic package. For a high-conductivity polymeric TIM, the adhesion strength between the TIM and its mating interfaces is typically weak, making the TIM susceptible to degradation when subjected to environmental stresses. At typical chip operating temperatures which are below the curing temperature of the TIM, a compressive force acts on the TIM at the chip center due to the CTE mismatch between the die and the organic chip carrier. Conversely at high BGA(Ball Grid Array) or card-attach reflow temperatures, the TIM center is under tension and the TIM tends to either cohesively separate or adhesively separate from the interfaces. Also, during moisture soaking, such as 85C/85%RH, the organic chip carrier absorbs moisture and expands. The hygroscopic expansion of the organic chip carrier is of the same order of magnitude as the thermal expansion. This expansion reduces the compressive force acting on the TIM, and for certain package constructions, this can lead to degradation of thermal performance. In this paper, the delamination mechanism of a polymer-based thermal interface material in an organic package during reflow and moisture soaking is investigated. The in-situ deformation of the TIM bondline was measured by a digital image correlation (DIC) method on a cross-sectioned part. The TIM bondline deformation was also captured by a digital camera. The coefficients of thermal expansion and hygroscopic expansion for different organic materials were measured, and a finite element analysis of the hygroscopic expansion and TIM bondline deformation was conducted. The affect of T&H stress was analyzed using an equivalent CTE concept.

Thermal Development, Modeling and Characterization of the Cell Processor Module

Optimal package thermal design for todays high power processors is critical to meet demanding performance, cost, and reliability objectives. This paper describes the thermal characterization and development of the first generation CELL processor, developed jointly by Sony, Toshiba and IBM. The package not only provides the very high bandwidth necessary for electrical performance, but also achieves low thermal resistance to dissipate high power and maintain low die temperatures with superior reliability. The focus of the paper is the first level package. The target thermal resistance for the package is explained as determined from detailed 2nd level modeling and novel power map calculation and validation techniques are discussed. Thermal and mechanical modeling are used characterize the effects of the thermal interface material (TIM) on the thermal performance and mechanical response of the package. The thermal test strategy and the TIM characterization techniques are described. In summary, the paper describes the novel thermal modeling and characterization methodology used in the design process, allowing high heat flux in a low cost system application

Capacitors on organic modules: a new THB failure mode and method of detection

Multi-terminal low inductance capacitors (MTLICs) are used widely throughout the electronics industry to aid with voltage noise suppression and to manage high speed switching currents. They are implemented on system level cards as well as microprocessors and ASICs. MTLIC component dimensions are getting smaller with increased requirements on capacitance/inductance, driving more Ni plates (up to ∼160), thinner dielectrics and therefore resulting in an increased risk for failure in temperature, humidity and bias stressing. Traditionally, MTLICs have been more robust than the modules they are used on - but this may be changing.

Reliability analysis on epoxy based thermal interface subjected to moisture environment

A thermal challenge has been growing in microelectronics industry to dissipate more and more chip power. New thermal solutions have been developed in industry. High metal filled thermal compound is one of them. This kind of thermal compound often uses a polymer matrix such as epoxy as the metal carrier. This paper is to investigate the thermal reliability with the environmental exposure to temperature and humidity. A mathematical diffusion model with variables of temperature, humidity and exposure time is utilized to analyze the moisture content in the thermal compound. Experimental measurements on bonding strength have shown to decrease as the moisture level increases in the thermal interface bondline following an exponential curve. An acceleration model is also obtained for the moisture level in thermal interface. Combined with the mechanical modeling, the packaging products could be designed to achieve a reliable thermal performance in the field with the epoxy based thermal interface