Raed A. Sherif

Thermal analysis of a substrate with power dissipation in the vias

As power dissipation at the chip level increases, current levels through power distribution wires increase correspondingly. This current flow results in Joule heating in the package, which must be included in any sizing of the package cooling requirements. An analysis of the temperature field resulting from the Joule heating in a metal wire surrounded by a nonheat generating (electrically insulating) material is presented. Exact analytical solutions are given for when the heat generation rate is constant (independent of temperature) and linearly dependent on the temperature. Asymptotic solutions are given for arbitrarily temperature-dependent heat generation, when the insulating material thermal conductivity is much less than the thermal conductivity of the wire. A numerical example of practical interest is then considered. It is shown that neglecting the Joule heating in the wires can result in significant under-prediction of the temperature. The effect of temperature on the electrical resistivity of the wire is shown to be negligible. The phenomenon of thermal runaway is also examined using stability theory and is shown to be unimportant in practical circumstances. >

Transient thermal gradients across solder interconnections in electronic systems

The authors provide a thermal analysis for a component mounted on a carrier via solder interconnections, with emphasis on understanding how the thermal gradients across the solder interconnections develop during the power-on transient. A 1D model is sought for its simplicity, while the important features of the problem are kept intact. Closed-form solutions are obtained when the thermal mass of the component is much less than the thermal mass of the carrier. The asymptotic solutions are compared with the numerical solutions of the same set of equations. Finite-element solutions and experimental data are also obtained to assess the validity of the 1D model as a predictor of the thermal gradients across the solder interconnections. Results of the analysis show that the thermal gradients across the solder interconnections reach a maximum at some early time before steady-state conditions are reached and that the thermal induced transient stains can be several times worse than the steady-state strains. >