Fred G. Kuper

Using an SCR as ESD protection without latch-up danger

A properly designed Low-Voltage Triggering SCR has a four times better ESD performance than a conventional grounded-gate NMOST of the same width. But it does present a latch-up risk due to its low holding voltage. The holding voltage can be increased by using a larger anode-to-cathode spacing, but at very large spacings the ESD performance decreases. It is shown that a window in SCR anode-to-cathode spacing exists, for which the holding voltage is sufficiently large, while the excellent ESD protection properties are preserved.

Relation between product yield and plasma process induced damage

The impact of plasma process induced damage (charging) on the yield of products in 75-120 /spl Aring/ CMOS processes has been analyzed. It was shown that product yield loss is related to the threshold voltage shift of charging sensitive test structures and thus to charging. A simple model is introduced in which the charging related yield loss component of products is expressed by the attributes of antennas and the extent of charging. The proposed model is found to predict charging related yield loss using only one process dependent parameter, as is shown for various products.

Plasma-charging damage of floating MIM capacitors

In this paper, the mechanism of plasma-charging damage (PCD) of metal-insulator-metal (MIM) capacitors as well as possible protection schemes are discussed. A range of test structures with different antennas simulating interconnect layout variations have been used to investigate the mechanism of PCD of MIM capacitors. Based on the experimental results, two models are presented, describing the relation between the damage and the ratio of the area of the exposed antennas connected to the MIM capacitors plates. New design rules are proposed in order to predict and automatically flag possible PCD sites. Furthermore, layout solutions to reduce PCD are suggested.

Analysis of the electrical breakdown in hydrogenated amorphous silicon thin-film transistors

Electrical breakdown induced by systematic electrostatic discharge (ESD) stress of thin-film transistors used as switches in active matrix addressed liquid crystal displays has been studied using electrical measurements, electrical simulations, electrothermal simulations, and postbreakdown observations. Breakdown due to very short pulses (up to 1 /spl mu/s) shows a clear dependence on the channel length. A hypothesis that electrical breakdown in the case of short channel TFTs is due to the punch-through is built on this dependence and is proved by means of electrical simulations. Further, the presence of avalanche breakdown in amorphous silicon thin-film transistors is simulated and confirmed. It is finally assumed that the breakdown is a thermal process. Three-dimensional (3-D) electrothermal simulations are performed in the static and transient regime, confirming the location of the breakdown spot within the TFT from the electrical simulations and postbreakdown observations.

Investigations on double-diffused MOS (DMOS) transistors under ESD zap conditions

In this paper we analyzed, through experiments and 2D simulations, the behaviour under high reverse voltages of a DMOS transistor. It turned out that the drift diffusion region (resistor) between the drain contact and p-diffusion region (PI) plays an important role both in the switching-on of the parasitic bipolar structure and in the failure mechanism.

Fast thermal cycling-enhanced electromigration in power metallization

Multilevel interconnects used in power ICs are susceptible to short circuit failure due to a combination of fast thermal cycling and electromigration stresses. In this paper, we present a study of electromigration-induced extrusion short-circuit failure in a standard two level metallization currently used in power ICs and in particular the effect of fast thermal cycling on the subsequent electromigration lifetime. A special test chip was designed, in which the electromigration test structure is integrated with a heating element and a diode as temperature sensor in order to generate fast temperature swings and to monitor them. Experimental results showed that with the introduction of fast thermal cycling as a preconditioning, the electromigration lifetime is significantly reduced. We observed that the reduction of the electromigration lifetime depends on the stress time, temperature range and the minimum temperature. Electromigration simulations using a two-dimensional simulator confirm the extrusion short circuit as failure mechanism.

Modelling of the reservoir effect on electromigration lifetime

Electromigration behaviour in W-plug/metal stripe structures is different from conventional metal-strip structures because there is a blocking boundary formed by the immobile W-plug in the contact/via. Electromigration failures occur more readily close to the W-plug than in metal-strip structures because metal ions are forced away from the contacts/vias by electric current, blocking the contacts/vias area. Several works have reported electromigration lifetime of multiple level interconnects to be influenced by the presence of a reservoir around the contacts/vias. Reservoirs are metal parts that are not or are hardly conducting current that act as a source to provide atoms for the area around the blocking boundary where the atoms migrate away due to the electric current. Interconnect lifetime can be prolonged by using the reservoirs, called the reservoir effect. 2D simulation of the effects of reservoirs has been performed. The stress build-up during electromigration in the contact area can be simulated for several configurations, separating the effects of overlap, total reservoir area, the reservoir layout directions (vertical and horizontal), number of contacts/vias and contact/via placement. It is very useful for IC design rules to estimate which parameters are important for IC reliability. In this study, we considered the critical stress that the metal line can sustain before void formation as failure criterion. The failure time is determined by the time to reach the critical stress.

Progressive degradation in a-Si: H/SiN thin film transistors

In this paper we present the study of gate-stress induced degradation in a-Si:H/SiN TFTs. The drain current transient during gate bias stress (forward or reverse bias) and subsequent relaxation cannot be fitted with the models existent in the literature but it shows to be described by a progressive degradation model (PDM). According to PDM the degradation of the electrical response is a combined effect of a fast interface traps generation and a slow charge trapping at the created defect sites and existing bulk defects in a-SiN:H transitional region.

Estimation of the impact of electrostatic discharge on density of states in hydrogenated amorphous silicon thin-film transistors

The objective of this letter is to give an estimation of the impact of an electrostatic discharge (ESD) stress on the density of states (DOS) within the energy gap of hydrogenated amorphous silicon (a-Si:H) thin-film transistors. ESD stresses were applied by means of a transmission line model tester. The DOS in the a-Si:H was determined by Suzukis algorithm using field-effect conductance measurements. A comparison of stressed and unstressed devices shows that there is a threshold ESD stress voltage, below which there is no damage. Above the threshold stress level, first an increase of the deep gap states is found and when stress is increased further, also in the tail states.

Test chip for detecting thin film cracking induced by fast temperature cycling and electromigration in multilevel interconnect systems

Temperature cycling in power ICs is a reliability hazard, even more so when electromigration is playing a role as well. The frequency of the temperature cycling is in the audio domain, which makes it impossible to test in environmental chambers. In the paper, the design and application of a novel test chip to study fast temperature cycling, electromigration and their interaction in multilevel interconnection systems is reported. Incorporated into the test chip are a heating element, a temperature sensor, and extrusion monitors. Simulation was used to study the initial stress distributions after processing and local temperature distributions in the test chip during the temperature transient. First experimental results have been obtained in the area of fast temperature cycling experiments (by using internal heating only) and electromigration experiments. Failure distributions and failure modes are discussed. Results indicate that on-chip cycling is a powerful tool to study reliability of power ICs under realistic conditions.