Hieu V. Nguyen

Fast temperature cycling and electromigration induced thin film cracking multilevel interconnection: experiments and modeling

There is an increasing reliability concern of thermal stress-induced and electromigration-induced failures in multilevel interconnections in recent years. This paper reports our investigations of thinfilm cracking of a multilevel interconnect due to fast temperature cycling and electromigration stresses. The fast temperature cycling tests have been performed in three temperature cycle ranges. The failure times aare represented well by a Weibull distribution. The distributions are relatively well behaved with generally similar slope (shape factor). The failure mechanism is well fitted by the Coffin-Manson equation indicating a uniform acceleration. The observation of cracking in the interlayre dielectric due to fast temperature cycling stress from failure analysis agrees well with the failure mechanism modeling and the calculated Coffin-Manson exponent. Electromigration experiments have shown that devices failed due to extrusion-shorts without increasing of resistance of metal line. The failure times are represented better by the Weibull distribution than by the lognormal distribution (normally used for electromigration data). A simulation of stress buil-up in metal line using an electromigration simulator confirmed that the cracking of interlayer dielectric is the weakest spot and most likely to cause electromigration failure.

Simulation and experimental characterization of reservoir and via layout effects on electromigration lifetime

As schrinking of feature size in integrated circuits and increasing of packing density continue, it becomes incrementally important to take into account the interconnect layout features which can limit the risk of electromigration failure and improve the reliability of intervonnect systems. However, hardly any information is available on the reservoir and via layout effects on electromigration. In this paper, we characterized the influence of via count and current crowding effects on electromigration lifetime in different via and reservoir layouts design through simulation and experiments. We observe a negligible difference in electromigration lifteime for structures having the same reservoir area, irrespective of the contact/via configuration. The effect of current crowding on electromigration lifetime after an increasing of the current density stress was still small. The highest tensile stress point obtained from simulations coincides with the experimentally found void locations.

Fast thermal cycling-enhanced electromigration in power metallization

Multilevel interconnects used in power ICs are susceptible to short circuit failure due to a combination of fast thermal cycling and electromigration stresses. In this paper, we present a study of electromigration-induced extrusion short-circuit failure in a standard two level metallization currently used in power ICs and in particular the effect of fast thermal cycling on the subsequent electromigration lifetime. A special test chip was designed, in which the electromigration test structure is integrated with a heating element and a diode as temperature sensor in order to generate fast temperature swings and to monitor them. Experimental results showed that with the introduction of fast thermal cycling as a preconditioning, the electromigration lifetime is significantly reduced. We observed that the reduction of the electromigration lifetime depends on the stress time, temperature range and the minimum temperature. Electromigration simulations using a two-dimensional simulator confirm the extrusion short circuit as failure mechanism.

Test chip for detecting thin film cracking induced by fast temperature cycling and electromigration in multilevel interconnect systems

Temperature cycling in power ICs is a reliability hazard, even more so when electromigration is playing a role as well. The frequency of the temperature cycling is in the audio domain, which makes it impossible to test in environmental chambers. In the paper, the design and application of a novel test chip to study fast temperature cycling, electromigration and their interaction in multilevel interconnection systems is reported. Incorporated into the test chip are a heating element, a temperature sensor, and extrusion monitors. Simulation was used to study the initial stress distributions after processing and local temperature distributions in the test chip during the temperature transient. First experimental results have been obtained in the area of fast temperature cycling experiments (by using internal heating only) and electromigration experiments. Failure distributions and failure modes are discussed. Results indicate that on-chip cycling is a powerful tool to study reliability of power ICs under realistic conditions.