Benno H. Krabbenborg

Nonisothermal device simulation using the 2D numerical process/device simulator TRENDY and application to SOI-devices

The electrical characteristics of modern VLSI and ULSI device structures may be significantly altered by self-heating effects. The device modeling of such structures demands the simultaneous simulation of both the electrical and the thermal device behavior and their mutual interaction. Although, at present, a large number of multi-dimensional device simulators are available, most of them are based on physical models which do not properly allow for heat transport and other nonisothermal effects. This paper, demonstrates that the numerical process/device simulator TRENDY provides a solid base for nonisothermal device simulation, as a physically rigorous device model of carrier and heat transport has been incorporated in the TRENDY program. With respect to the boundary conditions, it is shown that inclusion of an artificial boundary material relaxes some fundamental physical inconsistencies resulting from the assumption of ideal ohmic contact boundaries. The program TRENDY has been used for studying several nonisothermal problems in microelectronics. As an example, the authors consider an ultra-thin SOI MOSFET showing that the negative slopes in the V/sub ds//spl minus/I/sub ds/ characteristics are caused by the temperature-dependence of the electron saturation velocity. >

Layout to circuit extraction for three-dimensional thermal-electrical circuit simulation of device structures

In this paper, a method is proposed for extraction of coupled networks from layout information for simulation of electrothermal device behavior. The networks represent a three-dimensional (3-D) device structure with circuit elements. The electrical and thermal characteristics of this circuit representation are calculated with a circuit simulator. Spatial potential distributions, current flows, and temperature distributions in the device structure are calculated on the spatial coordinates. This simulation method can be placed between device simulation and (conventional) circuit simulation. It has been implemented in a circuit simulator and is demonstrated for simulation of self-heating in a bipolar low frequency power transistor. The main advantage of this simulation method is that not only the 3-D thermal behavior of the whole chip is simulated, but that this is also directly coupled to the electrical device behavior by means of the power dissipation and temperature distribution in the device. This offers the possibility for the circuit designer to simulate 3-D, coupled, thermal-electrical problems with a circuit simulator. As an example, the influence of the emitter contacting on the internal temperature and current distribution of a BJT is investigated.

Fast thermal cycling-enhanced electromigration in power metallization

Multilevel interconnects used in power ICs are susceptible to short circuit failure due to a combination of fast thermal cycling and electromigration stresses. In this paper, we present a study of electromigration-induced extrusion short-circuit failure in a standard two level metallization currently used in power ICs and in particular the effect of fast thermal cycling on the subsequent electromigration lifetime. A special test chip was designed, in which the electromigration test structure is integrated with a heating element and a diode as temperature sensor in order to generate fast temperature swings and to monitor them. Experimental results showed that with the introduction of fast thermal cycling as a preconditioning, the electromigration lifetime is significantly reduced. We observed that the reduction of the electromigration lifetime depends on the stress time, temperature range and the minimum temperature. Electromigration simulations using a two-dimensional simulator confirm the extrusion short circuit as failure mechanism.

Physics of electro-thermal effects in ESD protection devices

Damage in ESD protection devices can be caused by high local temperatures resulting from heat generation by an ESD pulse. In order to obtain physical insight into the process that leads to permanent damage, device simulations of coupled thermal and electrical behaviour have been performed. Additional to the potential and the electron and hole concentrations the lattice temperature is solved as a variable. Simulations of ESD pulses (forward bias) applied to a diode have been performed. The discharge mechanism could be visualised by using the coupled thermal/electrical model. Locations with considerable temperature rise that eventually lead to damage can be extracted from the calculated temperature distributions. Protection devices with optimum electrical and thermal characteristics can be designed by adjusting doping profiles and layout parameters. The buried layer of the protection device does not contribute in conducting current at high current levels. Therefore the buried layer is not functional in diodes that are subjected to ESD in forward bias. Measurements determining the ESD vulnerability of protection devices with and without buried layer confirm this fact.

3D Thermal/Electrical Simulation of Breakdown in a BJT Using a Circuit Simulator and a Layout-to-Circuit Extraction Tool

A method for the generation of circuit models for fast thermal-electrical simulation of 3D device structures with a circuit simulator is proposed. It has been used for simulation of the influence of layout parameters on the Safe Operating Area of a BJT and to study the mechanisms that start breakdown processes. For a thermally instable switch-on behaviour of a BJT, a comparison with measurements has been made.