Ton J. Mouthaan

Nonisothermal device simulation using the 2D numerical process/device simulator TRENDY and application to SOI-devices

The electrical characteristics of modern VLSI and ULSI device structures may be significantly altered by self-heating effects. The device modeling of such structures demands the simultaneous simulation of both the electrical and the thermal device behavior and their mutual interaction. Although, at present, a large number of multi-dimensional device simulators are available, most of them are based on physical models which do not properly allow for heat transport and other nonisothermal effects. This paper, demonstrates that the numerical process/device simulator TRENDY provides a solid base for nonisothermal device simulation, as a physically rigorous device model of carrier and heat transport has been incorporated in the TRENDY program. With respect to the boundary conditions, it is shown that inclusion of an artificial boundary material relaxes some fundamental physical inconsistencies resulting from the assumption of ideal ohmic contact boundaries. The program TRENDY has been used for studying several nonisothermal problems in microelectronics. As an example, the authors consider an ultra-thin SOI MOSFET showing that the negative slopes in the V/sub ds//spl minus/I/sub ds/ characteristics are caused by the temperature-dependence of the electron saturation velocity. >

Role of package parasitics and substrate resistance on the Charged Device Model (CDM) failure levels - An explantion and die protection strategy

With sownscaling of device dimensions and increased usage of automated handlers, Charged Device Model (CDM) type of Electrostatic Discharge (ESD) stress events are becoming the major readon for field returns in the Integrated Circuit (IC) industry. In the case of CDM stress, the IC is both the source of static charge and part od the discharge path. Hence CDM test results are greatly affected by the nature of the package, pin position and the location of the protection devices within the die. In this paper we present a systematic approach to understand the actual influence of these factors in the IC during a CDM event. The CDM test set-up is modeled using PSPICE circuit simulator and the discharge waveforms thus obtained are compared with the experimental observations. This model is then used to find the actual discharge current flowing through the die and the protection structures for different packages and pin positions. From this general protection strategy for CDM discharges, independent of the IC layout design is developed.

Analysis of the electrical breakdown in hydrogenated amorphous silicon thin-film transistors

Electrical breakdown induced by systematic electrostatic discharge (ESD) stress of thin-film transistors used as switches in active matrix addressed liquid crystal displays has been studied using electrical measurements, electrical simulations, electrothermal simulations, and postbreakdown observations. Breakdown due to very short pulses (up to 1 /spl mu/s) shows a clear dependence on the channel length. A hypothesis that electrical breakdown in the case of short channel TFTs is due to the punch-through is built on this dependence and is proved by means of electrical simulations. Further, the presence of avalanche breakdown in amorphous silicon thin-film transistors is simulated and confirmed. It is finally assumed that the breakdown is a thermal process. Three-dimensional (3-D) electrothermal simulations are performed in the static and transient regime, confirming the location of the breakdown spot within the TFT from the electrical simulations and postbreakdown observations.

Investigations on double-diffused MOS transistors under ESD zap conditions

In this paper we analyzed, through experiments and 2-D simulations, the behavior under high reverse voltages of a double-diffused MOS transistor. It turned out that the drift diffusion region (resistor) between the drain contact and p-diffusion region (PI) plays an important role both in the switching on of the parasitic bipolar structure and in the failure mechanism.

Investigations on double-diffused MOS (DMOS) transistors under ESD zap conditions

In this paper we analyzed, through experiments and 2D simulations, the behaviour under high reverse voltages of a DMOS transistor. It turned out that the drift diffusion region (resistor) between the drain contact and p-diffusion region (PI) plays an important role both in the switching-on of the parasitic bipolar structure and in the failure mechanism.

Physics of electro-thermal effects in ESD protection devices

Damage in ESD protection devices can be caused by high local temperatures resulting from heat generation by an ESD pulse. In order to obtain physical insight into the process that leads to permanent damage, device simulations of coupled thermal and electrical behaviour have been performed. Additional to the potential and the electron and hole concentrations the lattice temperature is solved as a variable. Simulations of ESD pulses (forward bias) applied to a diode have been performed. The discharge mechanism could be visualised by using the coupled thermal/electrical model. Locations with considerable temperature rise that eventually lead to damage can be extracted from the calculated temperature distributions. Protection devices with optimum electrical and thermal characteristics can be designed by adjusting doping profiles and layout parameters. The buried layer of the protection device does not contribute in conducting current at high current levels. Therefore the buried layer is not functional in diodes that are subjected to ESD in forward bias. Measurements determining the ESD vulnerability of protection devices with and without buried layer confirm this fact.

Estimation of the impact of electrostatic discharge on density of states in hydrogenated amorphous silicon thin-film transistors

The objective of this letter is to give an estimation of the impact of an electrostatic discharge (ESD) stress on the density of states (DOS) within the energy gap of hydrogenated amorphous silicon (a-Si:H) thin-film transistors. ESD stresses were applied by means of a transmission line model tester. The DOS in the a-Si:H was determined by Suzukis algorithm using field-effect conductance measurements. A comparison of stressed and unstressed devices shows that there is a threshold ESD stress voltage, below which there is no damage. Above the threshold stress level, first an increase of the deep gap states is found and when stress is increased further, also in the tail states.

The Time-Voltage Trade-off for ESD Damage Threshold in Amorphous Silicon Hydrogenated Thin-film Transistors

It is investigated whether damage or breakdown of the amorphous silicon thin film transistors (alpha-Si:H TFTs) under pulsed stress depends on the stress time. The drain of grounded gate TFTs has been stressed applying repeated square voltage pulses of different duration (100ns to 10s). The evolution and the mechanisms of the pre-breakdown degradation will be presented and discussed. Finally, the temperature distribution across an alpha-Si:H TFT under applied stress will be simulated by means of coupled electro-thermal simulations.

The Modeling of Resistance Changes in the Early Phase of Electromigration

Sensitive measurements of the evolution of the resistance of aluminum based metallisation stripes that have been electrically stressed with large current densities show a rather unpredictable initial change followed by a more or less linear increase (less than 1%) for a considerable period of time. Ultimately, breakdown will occur preceded by an erratic behavior of the resistance. This paper reviews existing models for these early changes. It reviews the importance of a generation term for vacancies separate from a divergence of flux term in the explanation of small resistance changes in these models and proposes an alternative view that explains the linear behavior of the resistance change and can also incorporate a variety of initial changes depending on initial mechanical stress conditions. In this model it is assumed that electron wind can create vacancies in the grain boundary regions that are further redistributed because of the electrical current. In this creation process less mobile damage is created, that contributes to the scattering of electrons and thus increases the resistance.

Zapping thin film transistors

It was expected that hydrogenated amorphous silicon thin film transistors (alpha-Si:H TFTs) behave similarly to crystalline silicon transistors under electrostatic discharge (ESD) stress. It will be disproved in this paper. This knowledge is necessary in the design of the transistors used in a ESD protection circuit. The goal of this paper was to identify and to model failure under ESD zap. The drain of grounded gate TFTs has been stressed applying repeated square voltage pulses of different duration (100 ns to 10 s). The evolution and the mechanisms of the pre-breakdown degradation will be presented and discussed. Finally, the temperature distribution across an alpha-Si:H TFT under applied stress will be simulated by means of coupled electro-thermal simulations.