Brice De Jaeger

New interface state density extraction method applicable to peaked and high-density distributions for Ge MOSFET development

A method for extracting parameters of weakly Fermi-level pinned germanium (Ge) capacitors is introduced. This method makes progress toward a more generally valid reliable interface state parameter extraction. Such a general method is needed to evaluate and explain the behavior of Ge MOS capacitors, which show characteristics deviating considerably from silicon. The encountered weak pinning confirmed by the new extraction method explains the degraded Ge nMOSFET performance.

AlGaN/GaN/AlGaN Double Heterostructures Grown on 200 mm Silicon (111) Substrates with High Electron Mobility

In this work, we demonstrate, for the first time, Al0.35GaN/GaN/Al0.25GaN double heterostructure field effect transistors on 200 mm Si(111) substrates. Thick crack-free Al0.25GaN buffer layers are achieved by optimizing Al0.75GaN/Al0.5GaN intermediate layers and AlN nucleation layers. The highest buffer breakdown voltage reaches 1380 V on a sample with a total buffer thickness of 4.6 µm. According to Van der Pauw Hall measurements, the electron mobility is 1766 cm2 V-1 s-1 and the electron density is 1.16×1013 cm-2, which results in a very low sheet resistance of 306±8 Ω/square.

Au-Free AlGaN/GaN Power Diode on 8-in Si Substrate With Gated Edge Termination

High-performance AlGaN/GaN diodes are realized on 8-in Si wafers with Au-free CMOS-compatible technology. The diodes are cointegrated on the same substrate together with the AlGaN/GaN metal-insulator-semiconductor high electron mobility transistors and with only one extra lithographic step. The diode anode and the transistor gate are processed together and the same metallization is used for both, avoiding extra metal deposition dedicated to the Schottky junction. A gated edge termination allows obtaining low reverse leakage current (within 1 μA/mm at -600 V), which is several orders of magnitude lower than the one of conventional Schottky diodes processed on the same wafer. Recess is implemented at the anode, resulting in low diode turn-on voltage values.

High FET Performance for a Future CMOS

In Germanium-based metal-oxide-semiconductor field-effect transistors, a high-quality interfacial layer prior to high-¿ deposition is required to achieve low interface state densities and prevent Fermi level pinning. In this letter, the physical and electrical properties of a Ge/GeO2/Al2O3 gate stack are investigated. The GeO2 interlayer grown by radical oxidation and the formation of a germanate (GeAlOX) layer at the interface provide a stable high-quality passivation of the Ge channel. High carrier mobilities (235 cm2/V·s for electrons and 265 cm2/V·s for holes) are demonstrated for a relatively low 3.7-nm equivalent oxide thickness (EOT), enabling the realization of a high-performance CMOS technology with potential EOT scaling.

\hbox{GeO}_{2}

In 1947, the first transistors were fabricated in Bell Labs using bulk germanium as the semiconducting material. For this work its inventors, John Bardeen and Walter Brattain shared the 1956 Nobel Prize in Physics, along with William Shockley. About a dozen years later, the integrated circuit was independently invented by Jack Kilby, who used Ge substrates, and by Robert Noyce, who used silicon, and for which Kilby received the 2000 Nobel Prize in Physics (Noyce had passed on in 1990). Germanium was the predominant material for solid state devices through the 1950s and early 1960s, but its use was largely replaced with silicon during the 1960s. There are a number of reasons for this shift, but the ready formation of a high quality thermal oxide (SiO2) for silicon as compared to the water soluble oxides for Ge (GeO, GeO2) and the difficulty this poses for device performance and integration is a major reason.

-Based Technology

In this paper, a further leakage reduction of AlGaN/GaN Schottky barrier diodes with gated edge termination (GET-SBDs) has been achieved by optimizing the physical vapor deposited TiN as the anode metal without severe degradation of ON-state characteristics. The optimized GET-SBD multifinger power diodes with 10 mm anode width deliver ~4 A at 2 V and show a median leakage of 1.3 μA at 25 °C and 3.8 μA at 150 °C measured at a reverse voltage of -200 V. The temperature-dependent leakage of Si, SiC, and our GaN power diodes has been compared. The breakdown voltage (BV) of GET-SBDs was evaluated by the variation of anode-to-cathode spacing (LAC) and the length of field plate. We observed a saturated BV of ~600 V for the GET-SBDs with LAC larger than 5 μm. The GET-SBD breakdown mechanism is shown to be determined by the parasitic vertical leakage current through the 2.8 μm-thick buffer layers measured with a grounding substrate. Furthermore, we show that the forward voltage of GET-SBDs can be improved by shrinking the lateral dimension of the edge termination due to reduced series resistance. The leakage current shows no dependence on the layout dimension LG (from 2 to 0.75 μm) and remains at a value of ~10 nA/mm. The optimized Au-free GET-SBD with low leakage current and improved forward voltage competes with high-performance lateral AlGaN/GaN SBDs reported in the literature.

Germanium: The Past and Possibly a Future Material for Microelectronics

This paper reports a comprehensive time dependent dielectric breakdown (TDDB) evaluation of recessed-gate devices with five different AlGaN barrier thicknesses with characteristics ranging from a D-mode MIS-HEMT to an E-mode MIS-FET. First, the fitted parameter β (the slope of the Weibull distribution) was smaller for a deeper recessed gate and larger for a thicker gate dielectric. Secondly, the extrapolated VG (criterium of 0.01% failures after 20 years) for the devices with Wg (gate width) = 10μm was lower when less AlGaN barrier remains under the gate. However, the extrapolated VG was increased when the AlGaN barrier was completely removed. Thirdly, a deeper recessed gate could result in a dominant percolation path due to a thinner gate dielectric on the sidewall of the gate recess edge. Fourthly, the Weibull distribution could scale with the gate width, indicating an intrinsic failure. Finally, the lifetime was extrapolated to 0.01% of failures for Wg=36mm at 150oC after 20 years by fitting the data with a power law or an exponential law to gate voltages of 4.9V and 7.2V, respectively.

Performance Optimization of Au-Free Lateral AlGaN/GaN Schottky Barrier Diode With Gated Edge Termination on 200-mm Silicon Substrate

We report on the fabrication and characterization of Au-free Ti/Al/TiN-based ohmic contacts on 200 mm AlGaN/GaN epilayers for power devices. Materials and processing used are fully compatible for integration of GaN-based devices in a Si platform. Contact resistance values as low as 0.62 Ωmm were measured for an optimum alloy temperature as low as 550 °C.

Time dependent dielectric breakdown (TDDB) evaluation of PE-ALD SiN gate dielectrics on AlGaN/GaN recessed gate D-mode MIS-HEMTs and E-mode MIS-FETs

In this paper, fully recessed-gate GaN MISFETs with two different gate dielectrics, i.e., plasma-enhanced atomic layer deposition (PEALD) SiN and ALD Al2O3 gate dielectric, are used to study the origin of positive bias temperature instability (PBTI). By employing a set of dedicated stress-recovery tests, we study PBTI during the stress and relaxation. Hence, a defect band model with different distributions of defect levels inside the gate dielectric is proposed, which can excellently reproduce the experimental data and provide insightful information about the origin of PBTI in GaN MISFETs. The results indicate that the serious PBTI in the device with PEALD SiN is mainly due to a wide distribution of defect levels (σ ~ 0.67 eV), centered below the conduction band of GaN (EC - 0.05 eV), and can be easily accessed by the channel carriers already at a low-gate voltage. On the other hand, ALD Al2O3 gate dielectric shows a narrower distribution of defects (σ ~ 0.42 eV), which are far from the conduction band of GaN (EC + 1.15 eV). This observations explain the improved PBTI reliability observed in devices with ALD Al2O3.

Au-free low temperature ohmic contacts for AlGaN/GaN power devices on 200 mm Si substrates

In this paper, three electrical techniques (frequency dependent conductance analysis, AC transconductance (AC-gm), and positive gate bias stress) were used to evaluate three different gate dielectrics (Plasma-Enhanced Atomic Layer Deposition Si3N4, Rapid Thermal Chemical Vapor Deposition Si3N4, and Atomic Layer Deposition (ALD) Al2O3) for AlGaN/GaN Metal-Insulator-Semiconductor High-Electron-Mobility Transistors. From these measurements, the interface state density (Dit), the amount of border traps, and the threshold voltage (VTH) shift during a positive gate bias stress can be obtained. The results show that the VTH shift during a positive gate bias stress is highly correlated to not only interface states but also border traps in the dielectric. A physical model is proposed describing that electrons can be trapped by both interface states and border traps. Therefore, in order to minimize the VTH shift during a positive gate bias stress, the gate dielectric needs to have a lower interface state density an...