Fredrik Ingvarson

Substrate resistance modeling for noise coupling analysis

Accurate substrate modeling is of utmost importance for substrate noise coupling analysis in mixed-signal circuits. In this paper we present a two-port Z-parameter model based on a physical description of the substrate surface potential. The Z-parameter model is expressed using a one-port semiempirical resistance model. This resistance model accurately describes the observed initial increase in resistance followed by the observed saturation as the contact separation increases. The Z-parameter model was compared to measurement data obtained from a set of CMOS test structures. The model fits measured results well, in contrary to when resistive networks are used to represent the substrate. Furthermore, we show that the substrate coupling between a digital circuit and an analog circuit does not have to become zero as the distance between the circuit blocks increases, instead the coupling between the circuits approaches a constant non-zero value.

A surface potential model for predicting substrate noise coupling in integrated circuits

Caution must be taken when designing circuits so that noise injected to and transmitted through the substrate does not reach and degrade the performance of sensitive circuitry present on the chip. In this paper we present a simple analytic substrate model for evaluating substrate noise coupling. The model can handle an arbitrary number of aggressor and victim devices on a multi-layered substrate with either biased or floating backside. The model has been validated by finite element calculations and measurements on test structures manufactured in a 0.35 /spl mu/m CMOS process, and it is shown that the model gives an accurate description of the substrate noise coupling. For example, the noise suppressing properties of guard rings have been evaluated.

Compact Spreading Resistance Model for Rectangular Contacts on Uniform and Epitaxial Substrates

We present a compact analytical spreading resistance model for substrate noise coupling analysis. The model can handle rectangular contacts on uniform substrates of finite thickness with a grounded backplane. In contrast to previously published compact models, the model does not require extraction of fitting parameters. The model is also scalable with the resistivity and thickness of the substrate, and with the contact size. The model is verified with extensive finite-element calculations, and the accuracy is shown to be good. We also show that the model can predict the spreading resistance on epitaxial substrates.

Extraction of emitter and base series resistances of bipolar transistors from a single DC measurement

A new procedure for extracting the emitter and base series resistances of bipolar junction transistors is presented. The parameters are extracted from a single measurement in the forward active region on one transistor test structure with two separate base contacts, making it a simple and attractive tool for bipolar transistor characterization. The procedure comprises two methods for extracting the emitter resistance and two for extracting the base resistance. The choice of method is governed by the amount of current crowding or conductivity modulation present in the intrinsic base region. The new extraction procedure was successfully applied to transistors fabricated in an in-house double polysilicon bipolar transistor process and a commercial 0.8-/spl mu/m single polysilicon BiCMOS process. We found that the simulated and measured Gummel characteristics are in excellent agreement and the extracted series resistances agree well with those obtained by means of HF measurements. By adding external resistors to the emitter and base and then extracting the series resistances, we verified that the two base contact test structure offers a simple means of separating the influence of emitter and base series resistances on the transistor characteristics.

A new procedure for extraction of series resistances for bipolar transistors from DC measurements

A new procedure for direct extraction of the base and emitter resistances is presented. The parameters are extracted from a single measurement on a transistor test structure with two separated base contacts. The proposed extraction procedure was successfully applied to transistors fabricated in a double polysilicon bipolar transistor process and a commercial 0.8 /spl mu/m single polysilicon BiCMOS process. The extracted values show good agreement with those obtained by means of high frequency measurements. Furthermore, the method was verified by simulations and extraction from modelled data using a distributed resistor-diode transistor model. Both emitter current crowding effects and conductivity modulation in the base are considered in the model. The comparison between measured and modelled transistor characteristics using the extracted values as input in the Gummel-Poon model also validates the DC extraction method. The method was found to be valid as long as conductivity modulation in the base is dominant over emitter current crowding effects as a cause for the decrease in the base resistance.

On DC modeling of the base resistance in bipolar transistors

The total base resistance R-BTot constitutes a crucial parameter in modeling bipolar transistors. The significant physical effects determining R-BTot are current crowding and conductivity modulation in the base, both causing reduction of R-BTot With increasing base current I-B. In this paper, it is shown that the reduction of R-BTot(I-B) With increasing I-B is directly related to the physical effect dominating in the base. A new model for R-BTot(I-B) is presented where a parameter alpha is introduced to account for the contributions of current crowding and conductivity modulation in the base. Theoretically, alpha is equal to 0.5 when conductivity modulation is dominant and close to 1.0 when current crowding is the most significant effect. This was verified by measurements and simulations using a distributed transistor model which accounts for the lateral distribution of the base current and the stored base charge. The model proposed for R-BTot(I-B) is very suitable for compact transistor modeling since it is given in a closed form expression handling both current crowding and conductivity modulation in the base. An accurate extraction procedure of the model parameters is also presented.

A new direct extraction algorithm for intrinsic Gummel-Poon BJT model parameters

A new two-step direct extraction algorithm for the intrinsic Gummel-Poon BJT model parameters is presented. In contrast to existing methods, both original and SPICE Gummel-Poon Early effect parameters can be extracted in a coupled and consistent manner. The base current is not involved in the extraction of the Early effect; thus the influence of nonideal base current need not be considered. This ensures proper extraction of the Early voltages, which is a necessary precursor to accurate determination of the remaining parameters. All parameters are determined from linear systems of equations using traditional least square techniques. An analysis of the distribution and number of data points used in the extraction to minimize sensitivity to noise is also performed.

A new test structure for parasitic resistance extraction in bipolar transistors

Design issues concerning the layout of the dual base terminal test structure are discussed and a new test structure is proposed which allows fast and simple extraction of the emitter, base and collector resistances in bipolar transistors. The structure is designed as a regular transistor, equipped with two base terminals for base and emitter resistance extraction and two collector terminals for collector resistance extraction. The structure has been successfully implemented in both double poly-Si and single poly-Si technologies. The extracted resistances agree well with those extracted by other methods. It is also shown that the use of an additional collector contact enables monitoring of the onset of the base push-out (Kirk) effect.

Extraction of the intrinsic base region sheet resistance in bipolar transistors

A new method for extracting the intrinsic base sheet resistance in bipolar transistors is presented. In contrast to existing methods, which give the sheet resistance at a given forward bias, the method proposed here allows the determination of the zero-bias sheet resistance of the intrinsic base which is an important parameter in both process characterization and circuit design. Furthermore, the new method is not restricted to a narrow range of biases and emitter widths as in existing methods, since the effects of current crowding, base conductivity modulation and base width modulation are accurately taken into account in the extraction procedure.

Properties and modeling of ground structures for reducing substrate noise coupling in ICs

Substrate noise can seriously degrade the performance of system-on-chip designs containing sensitive analog circuits together with noisy digital circuits. To reduce the coupling guard bands or guard rings are often used for protecting the analog circuitry. However, the efficiency of these ground structures is often not known on beforehand. Therefore, in this paper we investigate the noise reducing properties of different ground structures. It is shown that distributed ground structures are typically more efficient than localized ground structures due to smaller inter-contact influences. We also introduce two convenient measures of grounding efficiency, the global and local substrate potentials, and we present compact analytical models for these. The models are verified with numerical calculations and the accuracy is shown to be very good