Jan Grahn

Implanted collector profile optimization in a SiGe HBT process

Abstract Optimization of implanted collector doping profiles for a high-speed, low-voltage SiGe HBT process has been investigated experimentally and by device simulations. A low-energy antimony implantation has been combined with a standard selectively implanted collector using phosphorous, to achieve improved control of the collector doping profile. The simulations indicate that the narrow n-type doping peak formed by the antimony implantation allows the cut-off frequency f T to be increased without degrading the collector emitter breakdown voltage BV CEO . The fabricated devices demonstrate a highest f T of 60 GHz. Depending on the collector profile BV CEO values between 1.5 and 2 V were obtained.

Extraction of emitter and base series resistances of bipolar transistors from a single DC measurement

A new procedure for extracting the emitter and base series resistances of bipolar junction transistors is presented. The parameters are extracted from a single measurement in the forward active region on one transistor test structure with two separate base contacts, making it a simple and attractive tool for bipolar transistor characterization. The procedure comprises two methods for extracting the emitter resistance and two for extracting the base resistance. The choice of method is governed by the amount of current crowding or conductivity modulation present in the intrinsic base region. The new extraction procedure was successfully applied to transistors fabricated in an in-house double polysilicon bipolar transistor process and a commercial 0.8-/spl mu/m single polysilicon BiCMOS process. We found that the simulated and measured Gummel characteristics are in excellent agreement and the extracted series resistances agree well with those obtained by means of HF measurements. By adding external resistors to the emitter and base and then extracting the series resistances, we verified that the two base contact test structure offers a simple means of separating the influence of emitter and base series resistances on the transistor characteristics.

A low-complexity 62-GHz fT SiGe heterojunction bipolar transistor process using differential epitaxy and in situ phosphorus-doped poly-Si emitter at very low thermal budget

A low-complexity SiGe heterojunction bipolar transistor process based on differential epitaxy and in situ phosphorus doped polysilicon emitter technology is described. Silane-based chemical vapor d ...

Chemical vapor deposition of undoped and in-situ boron- and arsenic-doped epitaxial and polycrystalline silicon films grown using silane at reduced pressure

A nonselective epitaxial growth process for heterojunction bipolar transistors has been studied. The difference in growth rates for epitaxial and polycrystalline films could be used to monitor the ...

A new procedure for extraction of series resistances for bipolar transistors from DC measurements

A new procedure for direct extraction of the base and emitter resistances is presented. The parameters are extracted from a single measurement on a transistor test structure with two separated base contacts. The proposed extraction procedure was successfully applied to transistors fabricated in a double polysilicon bipolar transistor process and a commercial 0.8 /spl mu/m single polysilicon BiCMOS process. The extracted values show good agreement with those obtained by means of high frequency measurements. Furthermore, the method was verified by simulations and extraction from modelled data using a distributed resistor-diode transistor model. Both emitter current crowding effects and conductivity modulation in the base are considered in the model. The comparison between measured and modelled transistor characteristics using the extracted values as input in the Gummel-Poon model also validates the DC extraction method. The method was found to be valid as long as conductivity modulation in the base is dominant over emitter current crowding effects as a cause for the decrease in the base resistance.

On DC modeling of the base resistance in bipolar transistors

The total base resistance R-BTot constitutes a crucial parameter in modeling bipolar transistors. The significant physical effects determining R-BTot are current crowding and conductivity modulation in the base, both causing reduction of R-BTot With increasing base current I-B. In this paper, it is shown that the reduction of R-BTot(I-B) With increasing I-B is directly related to the physical effect dominating in the base. A new model for R-BTot(I-B) is presented where a parameter alpha is introduced to account for the contributions of current crowding and conductivity modulation in the base. Theoretically, alpha is equal to 0.5 when conductivity modulation is dominant and close to 1.0 when current crowding is the most significant effect. This was verified by measurements and simulations using a distributed transistor model which accounts for the lateral distribution of the base current and the stored base charge. The model proposed for R-BTot(I-B) is very suitable for compact transistor modeling since it is given in a closed form expression handling both current crowding and conductivity modulation in the base. An accurate extraction procedure of the model parameters is also presented.

Influence of transient enhanced diffusion of the intrinsic base dopant profile on SiGe HBT DC and HF characteristics

The influence of transient enhanced boron out-diffusion from the intrinsic base, caused by excess silicon interstitials created during the extrinsic base implantation, has been investigated for a non-selective SiGe HBT process. Devices with different designs of the extrinsic base region were fabricated, where some designs allowed part of the epitaxial base to be implanted with a high boron dose, hereby increasing the number of silicon interstitials close to the intrinsic device. These devices showed a marked degradation of DC characteristics and HF performance. 2D-device simulations were used to investigate the sensitivity in DC and HF parameters to vertical base profile changes. Good agreement was obtained between measured and simulated DC and HF characteristics.

A new test structure for parasitic resistance extraction in bipolar transistors

Design issues concerning the layout of the dual base terminal test structure are discussed and a new test structure is proposed which allows fast and simple extraction of the emitter, base and collector resistances in bipolar transistors. The structure is designed as a regular transistor, equipped with two base terminals for base and emitter resistance extraction and two collector terminals for collector resistance extraction. The structure has been successfully implemented in both double poly-Si and single poly-Si technologies. The extracted resistances agree well with those extracted by other methods. It is also shown that the use of an additional collector contact enables monitoring of the onset of the base push-out (Kirk) effect.

Extraction of the intrinsic base region sheet resistance in bipolar transistors

A new method for extracting the intrinsic base sheet resistance in bipolar transistors is presented. In contrast to existing methods, which give the sheet resistance at a given forward bias, the method proposed here allows the determination of the zero-bias sheet resistance of the intrinsic base which is an important parameter in both process characterization and circuit design. Furthermore, the new method is not restricted to a narrow range of biases and emitter widths as in existing methods, since the effects of current crowding, base conductivity modulation and base width modulation are accurately taken into account in the extraction procedure.

A procedure for characterizing the BJT base resistance and Early voltages utilizing a dual base transistor test structure

The pinched-base extraction technique is investigated in detail. The separation of extrinsic and intrinsic base resistances utilizing the dependence of these resistances on transistor geometry is discussed. Uncertainties in extracted parameter values and deviations between nominal and real device geometry are shown to be two major problems associated with separation of the base resistance components. Also, the use of the extracted resistances in compact transistor modeling for circuit simulation is discussed. It is shown that the intrinsic base resistance obtained using the pinched-base technique does not necessarily translate directly into a compact model parameter. The dual base test structure used for resistance extraction is also used for extraction of the voltage dependent Early voltages. In contrast to previous methods which require the extrinsic base resistance, the method presented here does not require this parameter which, as shown here, can be difficult to extract. By using the new extraction method on transistors with different emitter widths, it was observed that the Early voltages decrease as the emitter width is increased and saturates at some value for very wide emitters. An explanation to the observed behavior, supported by device structure simulations, is also given.