Lars-Ake Ragnarsson

Origin of NBTI variability in deeply scaled pFETs

The similarity between Random Telegraph Noise and Negative Bias Temperature Instability (NBTI) relaxation is further demonstrated by the observation of exponentially-distributed threshold voltage shifts corresponding to single-carrier discharges in NBTI transients in deeply scaled pFETs. A SPICE-based simplified channel percolation model is devised to confirm this behavior. The overall device-to-device ΔVth distribution following NBTI stress is argued to be a convolution of exponential distributions of uncorrelated individual charged defects Poisson-distributed in number. An analytical description of the total NBTI threshold voltage shift distribution is derived, allowing, among other things, linking its first two moments with the average number of defects per device.

Ultra low-EOT (5 Å) gate-first and gate-last high performance CMOS achieved by gate-electrode optimization

A novel gate first integration approach enabling ultra low-EOT is demonstrated. HfO₂ based devices with a zero interface layer and optimized gate-electrode is used to achieve EOT and T_inv values of ˜5 Å and ˜8 Å respectively for both n and pMOS devices. The drive currents at I_off=100 nA/μm with V_DD=1 V is 1.4 mA/μm and 0.6 mA/μm (no SiGe source/drain) for n and pMOS respectively. The technology further offers low n/pMOS V_T of 0.3/-0.4V, good V_T-uniformity, and V_T-matching and very high cutoff frequencies at ˜290-340 GHz for 38 nm nMOS devices. A replacement poly gate process is used to further improve upon the pMOS effective work function. TDDB lifetimes over 10 years are reported while BTI indicates potential reliability challenges.

Impact of single charged gate oxide defects on the performance and scaling of nanoscaled FETs

We report extensive statistical NBTI reliability measurements of nanoscaled FETs of different technologies, based on which we propose a 1/area scaling rule for the statistical impact of individual charged gate oxide defects on the electrical characteristic of deeply scaled transistors. Among the considered technologies, nanoscaled SiGe channel devices show smallest time-dependent variability. Furthermore, we report comprehensive measurements of the impact of individual trapped charges on the entire FET ID-VG characteristic. Comparing with 3D atomistic device simulations, we identify several characteristic behaviors depending on the interplay between the location of the oxide defect and the underlying random dopant distribution.

Insight Into N/PBTI Mechanisms in Sub-1-nm-EOT Devices

New insights into the negative/positive bias temperature instability (N/PBTI) degradation mechanisms in the sub-1-nm equivalent oxide thickness (EOT) regime are presented in this paper. The electric field requirements suggested by the International Roadmap for Semiconductors demand an even higher value in the sub-1-nm-EOT regime, which is practically difficult to meet with the increased hole trapping mechanism involved. Thus, a fixed electric field target of 5 MV/cm is considered as well here, which might be a reasonable target to achieve. The sub-1-nm-EOT devices in this paper are obtained by adopting a thinner TiN metal gate inducing Si in-diffusion and reducing the interfacial oxide layer thickness. NBTI degradation follows an isoelectric field model in over an EOT of 1 nm due to the degradation mechanism of Si/SiO_2 interface state generation combined with a hole trapping mechanism. However, in the sub-1-nm-EOT regime, the probability of hole trapping into the gate dielectric increases, and it is strongly dependent on the thickness of the interfacial oxide layer. Several experimental proofs of this increased bulk defect effect are shown in this paper. In addition, the bulk defect affecting NBTI is shown to be mostly a preexisting defect, although the permanently generated defects are relatively higher in sub-1-nm-EOT devices. Therefore, NBTI in the sub-1-nm-EOT regime faces the lifetime limit by both electric field dependence and increased degradation by increased hole trapping into bulk defects. Further, we found a minimum interfacial layer thickness of 0.4 nm that is required to prevent the accelerated NBTI degradation by increased direct tunneling. The main degradation mechanism of PBTI in sub-1-nm EOT is the electron trapping into bulk defects, which is the same as in over 1-nm-EOT devices. This enables us to modulate the bulk defect energetic locations in the oxide and to improve PBTI.

Achieving Conduction Band-Edge Effective Work Functions by

Conduction band-edge effective work functions (phi_m,eff) are demonstrated with TaC_x and TiN by means of La₂O₃ capping of HfSiO_x in a gate-first process flow with CMOS-compatible thermal budget. With TaC_x, a 10- Aring-thick La₂O₃ cap results in a phi _m,eff of 3.9 eV with a low equivalent oxide thickness (EOT) increase (1-2 Aring) and unaffected electron mobility. With TiN, non-nitrided La₂O₃ capping results in a smaller phi_m,eff reduction at a larger EOT increase, while with post-cap nitridation, the TiN phi_m,eff is lower at a smaller EOT increase. Results show that the choice of metal and nitridation conditions have significant effects on La₂O₃ capped stacks

\hbox{La}_{2}\hbox{O}_{3}

It is shown that the inversion charge in MOSFETs can be directly measured by a variant of the charge pumping (C-P) technique in long channel devices (inversion-charge pumping (ICP)). This new technique is used to demonstrate that charge trapping and net-fixed charge in n-channel MOSFETs with SiO/sub 2//HfO/sub 2/ dual layer gate dielectrics are not the primary cause for the strong mobility degradation.

Capping of Hafnium Silicates

The authors demonstrate high-performing n-channel transistors with a HfO2/TaN gate stack and a low thermal-budget process using solid-phase epitaxial regrowth of the source and drain junctions. The thinnest devices have an equivalent oxide thickness (EOT) of 8 Aring, a leakage current of 1.5 A/cm2 at VG=1 V, a peak mobility of 190 cm2/Vmiddots, and a drive-current of 815 muA/mum at an off-state current of 0.1 muA/mum for VDD=1.2 V. Identical gate stacks processed with a 1000-degC spike anneal have a higher peak mobility at 275 cm2/Vmiddots, but a 5-Aring higher EOT and a reduced drive current at 610 muA/mum. The observed performance improvement for the low thermal-budget devices is shown to be mostly related to the lower EOT. The time-to-breakdown measurements indicate a maximum operating voltage of 1.6 V (1.2 V at 125 degC) for a ten-year lifetime, whereas positive-bias temperature-instability measurements indicate a sufficient lifetime for operating voltages below 0.75 V

Direct measurement of the inversion charge in MOSFETs: application to mobility extraction in alternative gate dielectrics

In this paper, the electrical performance of high-k dielectrics for future technology generations is discussed. Despite major achievements in the development of high-k dielectrics, such as the gate leakage reduction - which is the main motivation why high-k dielectrics are being introduced - and the successful integration in small MOSFET devices, some major problems remain to be solved. These problems are threshold voltage control and stability, mobility and drive current performance and reliability problems. Significant progress in the performance of these layers was made by the use of engineered interfaces and optimized high-k stacks.

Electrical characteristics of 8-/spl Aring/ EOT HfO/sub 2//TaN low thermal-budget n-channel FETs with solid-phase epitaxially regrown junctions

The multi-gate architecture is considered as a key enabler for further CMOS scaling. FinFETs can readily be manufactured on SOI or bulk substrates. We report for the first time an extensive benchmark of their critical electrical figures of merit. Both alternatives show better scalability than PLANAR CMOS and exhibit similar intrinsic device performance. Introducing SOI substrates and low doped fins results in lower junction capacitance, higher mobility and voltage gain with reduced mismatch. Using an optimized integration to minimize parasitics we demonstrate high-performing FinFET ring-oscillators with delays down to 10ps/stage for both SOI and bulk FinFETs and working SRAM cells at VDD=1.0V.

Achievements and challenges for the electrical performance of MOSFETs with high-k gate dielectrics

We report low V<inf>t</inf> (V<inf>t,Lg=1µm</inf>=±0.26V) high performance CMOS devices with ultra-scaled T<inf>inv</inf> down to T<inf>inv</inf>∼8Å using a gate-first dual Si/SiGe channel low-complexity integration approach. Compared to a dual dielectric cap gate-first integration scheme, the devices fabricated with the novel scheme show for the same high-k/metal gate stack (1) 3Å reduction in nMOS and pMOS T<inf>inv</inf> (2) 220mV lower long channel pMOS V<inf>t</inf> (3) 21%/12% pMOS/nMOS drive current increase at I<inf>off</inf>=100nA/µm and (4) 50% improvement in long channel pMOS Vt variability. For a fixed T<inf>inv</inf> of 12Å, a 4 times higher hole mobility and 350mV increase in NBTI 10years lifetime operating voltage are obtained.