Fritz Redeker

Development of a production worthy copper CMP process

A chemical mechanical polishing (CMP) process for copper damascene structures has been developed and characterized on a second generation, multiple platen polishing tool. Several formulations of experimental copper slurries containing alumina abrasive particles were evaluated for their selectivity of copper to Ta, TaN and PETEOS films. The extent of copper dishing and oxide erosion of these slurries is investigated with various process parameters such as slurry flow rate, platen speed and wafer pressure. The amount of dishing and erosion is found to be largely dependent on process parameters as well as the slurry composition. It is shown that the extent of oxide erosion and copper dishing can be significantly reduced by using a two slurry copper polish process (one slurry to polish copper and another to polish barrier layers) in conjunction with an optical end-point detection system.

High-aspect-ratio trench etching

A high aspect ratio (> 15:1), sub-micron, deep capacitor trench process is demonstrated in an 8 inch Applied Materials P5000E magnetically enhanced reactive ion etcher (MERIE) using HBr/NF3/He-O2 chemistry. Through the insertion of ferro-magnetic sheet material into the pedestal, sub-micron trenches can be etched to depths greater than 10 micrometers , with etch rates > 6000 angstroms/min, uniformity < +/- 5%, profile uniformity 89 +/- 0.5 degree(s) and selectivity to oxide > 40:1. The importance of the wafer surface temperature on trench etch properties is established. Studies indicate that there is a threshold temperature below which the chosen recipe would need to be modified to produce satisfactory trenches.

Post-CMP Cleaning

Abstract Chemical mechanical planarization has been widely applied to selectively remove materials for topography planarization and device structure formation in semiconductor manufacturing. The selective material removal is achieved by using chemical reaction and mechanical abrasion with slurries containing unique chemical formulations and large numbers of abrasive particles. During polishing, chemical reaction products and mechanical wear debris are generated. Slurry particles and polishing byproducts are pressed onto wafer surface. During wafer transferring from polisher to cleaner, contaminants are adhered onto wafer surface. Post-CMP cleaning is required to remove particles, organic residues, and metallic contaminants from wafers with different surface, chemical, and mechanical properties in various geometric features, without generating scratches, water marks, surface roughness, corrosion, and dielectric constant shift. In this chapter, a review of post-CMP cleaning for various CMP applications is provided with a focus on cleaning technology, cleaning chemistry, and cleaning process. Common defect modes and generation mechanism are discussed. Post-CMP cleaning plays a critical role in meeting stringent CMP defect and device reliability/yield requirement.

Chemical mechanical cleaning for CMP defect reduction

As device geometry shrinks, defect reduction for yield improvement has always been the key focus in CMP process qualification. New post-CMP cleaning capability is demanded for meeting defect reduction requirement. To address the cleaning challenges in advanced nodes, innovation is needed. This paper reviews the innovation of Applied Materials CMP in post-CMP cleaning, from Megasonic cleaning for improving particle removal efficiency, to single wafer IPA vapor dryer for achieving water-mark free drying, and to a unique chemical mechanical cleaning (PreClean) technology for fulfilling the requirement of organic residue, particle, and nano-sized slurry ball removal in sub 10nmand beyond.

Polishing and Cleaning of Low K Dielectric Material for ild and Damascene

This paper describes CMP challenges in development of copper-low k process technology. As copper/oxide or copper/FSG backend schemes are being implemented successfully in early manufacturing, development focus has shifted to Cu/OSG (organo-silicate glass) integration development. Cu-OSG presents unique challenges with CMP integration, as these films tend to have much lower hardness than silicon dioxide. Significant process challenges have to be overcome prior to successfully implementing CMP process which does not mechanically damage the softer films and at the same time can achieve planarization requirements expected from CMP process. In addition, the OSG films tend to be hydrophobic leading to a need for developing improved cleaning processes/consumables. It was determined that Applied Materials ElectraPolishTM barrier slurry is extendable to OSG films. Good removal rate and removal profile can be achieved with ElectraPolishTM slurry. A proprietary cleaning solution reduced defect counts by 2 orders of magnitude as detected by SurfScan SS6200 on blanket OSG wafers. The same cleaning solution can be applied to copper/low-k patterned damascene wafers to clean both copper and dielectric surface. Polished OSG films have RMS roughness less than 2 angstroms and copper surface roughness about 5 angstroms with good surface finish. Blanket and patterned wafer results are presented to demonstrate final capability. Future directions for process enhancement are suggested.