Akihiro Horibe

Through silicon via process for effective multi-wafer integration

We propose a novel 3D integration method, called Vertical integration after Stacking (ViaS) process. The process enables 3D integration at significantly low cost, since it eliminates costly processing steps such as chemical vapor deposition used to form inorganic insulator layers and Cu plating used for via filling of vertical conductors. Furthermore, the technique does not require chemical-mechanical polishing (CMP) nor temporary bonding to handle thin wafers. The integration technique consists of forming through silicon via (TSV) holes in pre-multi-stacked wafers (> 2 wafers) which have no initial vertical electrical interconnections, followed by insulation of holes by polymer coating and via filling by molten metal injection. In the technique, multiple wafers are etched at once to form TSV holes followed by coating of the holes by conformal thin polymer layers. Finally the holes are filled by using molten metal injection so that a formation of interlayer connections of arbitrary choice is possible. In this paper, we demonstrate 3-chip-stacked test vehicle with 50 × 50 μm-square TSVs assembled by using this technique.

TSV diagnostics by X-ray microscopy

TSV (Through Silicon Via) is one of the key elements for building 3D integrated silicon devices with high bandwidth interconnections. In this paper, we propose a diagnostic method for TSV defects by using X-ray projection microscopy. By optimizing the image contrast of the X-ray projection micrographs in reference to its X-ray intensity histogram, we could obtain the small defect features in TSVs fast and non-destructively. Comparison between this X-ray observation and the destructive cross sectional observation agreed very well. We also extended the implementation of this X-ray microscope diagnostic method to 8-in. full wafer observation. We investigated the wafers with copper-filled TSVs with 80 µm and 20 µm diameters, and confirmed the feasibility of this method for an in-line process monitoring.

Vertical integration after stacking (ViaS) process for low-cost and low-stress 3D silicon integration

A low-cost assembly method is necessary for widespread use of 3D silicon integration. We have been proposing a vertical Si integration process, called Vertical integration after Stacking (ViaS), intended to lower costs, lower stress, and increase yields. The ViaS process uses a polymer insulator and a solder filling technique instead of a SiO2 insulator and Cu plating. Different from conventional processes, each vertical electrical conductor is continuous from the bottom to the top through the silicon stack and the conductor is surrounded with polymer insulators with a low-Youngs modulus. As a result, this ViaS process will greatly decrease the stress in vertical conductors and silicon substrates and increase reliability. In this paper, we present prototyped Si stacks with the ViaS process and the analyzed results on their stress characteristics. The results obtained show significant stress reductions at vertical connections between the layers, which would increase the reliability. These features of 3D stacks by the ViaS process will significantly contribute to expanding the range of 3D-integrated device applications.

Fine-pitch solder joining for high density interconnection

We have studied a thermo-compression bonding method for high density interconnections. Fluxes are commonly used in conventional solder bonding. However, flux applications have several issues such as the void generation in solder and the flux residue remaining between bumps. These could degrade their reliabilities seriously when the bump pitch becomes small since these features do not scale to bump-pitch dimensions. In this paper, we present the experimental results on the investigation of flux-less bonding with a hydrogen radical plasma treatment in fine-pitch bump joining, in order to eliminate these issues. Experimental results of 10 μm-pitch solder bonding showed good metallic continuities at joining interfaces without any organic residues, showing advantages of flux-less bonding on fine-pitch solder bonding.

Thermal stress analysis of die stacks with fine-pitch IMC interconnections for 3D integration

The thermo-mechanical reliability of stacked die structures is a critical issue in 3D packaging. The assessment of the stress and the warpage of silicon dies in 3D stacked structures become important in achieving low-stress and low-warpage 3D packaging. However the parametric analyses of thermal stress and die-warpage by rigorous finite element analysis can be time consuming for 3D systems, since it involves many layers of materials such as silicon dies and organic layers. In this paper, we used the finite element method (FEM) with a simple 2D model to analyze the stress under thermal cycling condition on the die stack system and applied the 1D multilayered beam theory to perform parametric analyses of the die-warpage for the thermal stress condition. We used a 3D slice model to analyze the stress in the intermetallic compound (IMC) joints. The die-warpage values and the high stress sites in stacked structures obtained by these analyses were consistent with the measured data and experimental observations from the thermal cycle tests on full-area-array 40 μm bump pitch stacked die test vehicles with intermetallic compound joints.

Thermal stress and die-warpage analyses of 3D die stacks on organic substrates

Packaging of 3D die stacks on organic laminates is a low-cost approach to achieve devices with high density I/O and short wiring delays. However, the large mismatch in coefficients of thermal expansion between components in the package causes deformation and high stress in the constituting elements. The components such as thin dies, metal through silicon vias, fine-pitch interconnections are susceptible to failures under high stress. In this study, we assessed the potential challenges in packaging of 3D die stacks on organics laminates. The challenges are the die-warpage in assembling and the thermal stress on fine-pitch interconnections in devices reliability. We used test vehicles with 40μm pitch full-area-array interconnections for the study. We observed a significant warpage in the stacked 50μm thick silicon dies at room temperature. We measured the warpage at several temperatures and analyzed using the multilayered beam theory. The simulated values assuming zero warpage at the melting temperature of the SnAgCu solder (220°C), were consistent with the measured values. The analysis showed that the die-warpage occurs due to the mismatch of CTE between silicon dies with Cu-TSVs and the top die without any TSVs. Previous study of the 40μm pitch test vehicle showed that one could widen the selection range of the mechanical properties of the interchip underfill materials by optimizing the silicon interposer thickness. In this study, we extended the analysis to the die stacks with interconnection pitch of 20μm and 80μm and show that one can achieve low-stress packaging by optimization of the silicon die thicknesses.

High density 3D integration by pre-applied Inter Chip Fill

28,561 bumps/die were electrically connected by Stack Joining method using pre-applied Inter Chip Fill resin.

Solder Injected through Via for Multi Stacked Wafers

Low cost through silicon via (TSV) technology is a key enabler for the future performance growth of various semiconductor devices. Deep etching and solder filling for TSV through pre-stacked silicon wafers make the TSV process much simpler. Polymer insulator also contributes to stress reduction and conformal insulation. In this paper, we investigate the barrier effect of polymer insulators on metal diffusion through the polymer into a silicon device by using various simple test specimens. It is found that although tin and indium showed some diffusion in the polymer materials, gold, silver, and bismuth showed little diffusion after excess annealing. We conclude that various popular solders such as SnAg, SnBi, and SnIn can be adopted as the solder via material with low risk of metal contamination in silicon.

Wafer-level non conductive films for exascale servers

Wafer-Level Non Conductive Films (WLNCFs) were evaluated as a potential underfill solution for future exascale server packages. The fundamental chip-joining ability and reliability on a small die package were tested. The fillet shapes, fillet overcoating, adhesion strength, and simplifications of the chip joining conditions, and the thermomechanical stresses in relation to the lower CTE substrate were evaluated and assessed for the future advanced packages.

Thermally enhanced pre-applied underfills for 3D integration

One of the biggest challenges for future high-performance three dimensional (3D) integrated devices is heat removal from the stacked dies. In this study, thermally enhanced pre-applied type underfills were studied. These materials were formulated considering fillet cracks and delaminations that appeared in thermal cycling tests on 2D organic package. Finally, the applicability for 3D integration processing with the new material was evaluated on a 3D test vehicle assembly.